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参数资料
| 型号： | NAND01GR3B3BV1T |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| 封装： | 12 X 17 MM, 0.65 MM HEIGHT, PLASTIC, USOP-48 |
| 文件页数： | 14/59页 |
| 文件大小： | 998K |
| 代理商： | NAND01GR3B3BV1T |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Read
The Cache Read operation is used to improve the
read throughput by reading data using the Cache
Register. As soon as the user starts to read one
page, the device automatically loads the next page
into the Cache Register.
An Cache Read operation consists of three steps
(see Table 10.):
1.
One bus cycle is required to setup the Cache
Read command (the same as the standard
Read command)
2.
bus cycles are then required to input the Start
Address
3.
One bus cycle is required to issue the Cache
Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a
page (Column Address = 00h, see Table 8. and
Table 9.). This allows the data to be output unin-
The Ready/Busy signal can be used to monitor the
start of the operation. During the latency period the
Ready/Busy signal goes Low, after this the Ready/
Busy signal goes High, even if the device is inter-
nally downloading page n+1.
Once the Cache Read operation has started, the
Status Register can be read using the Read Status
Register command.
During the operation, SR5 can be read, to find out
whether the internal reading is ongoing (SR5 =
‘0’), or has completed (SR5 = ‘1’), while SR6 indi-
cates whether the Cache Register is ready to
download new data.
To exit the Cache Read operation an Exit Cache
Read command must be issued (see Table 10.).
If the Exit Cache Read command is issued while
the device is internally reading page n+1, page n
will still be output, but not page n+1.
Figure 11. Cache Read Operation
I/O
RB
Address
Inputs
ai08661
00h
Read
Setup
Code
31h
Cache
Read
Confirm
Code
Busy
tBLBH1
(Read Busy time)
1st page
Data Output
2nd page
3rd page
last page
34h
Exit
Cache
Read
Code
Block N
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| NAND08GW3B2CZC1 | 1G X 8 FLASH 3V PROM, 35 ns, PBGA63 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GR3M0AZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZB5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0AZC5F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| NAND01GR3M0BZB5E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
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