参数资料
| 型号： | NB7L14MNG |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/10页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER 1:4 8GHZ 16-QFN |
| 标准包装： | 123 |
| 系列： | GigaComm™ |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | LVPECL |
| 频率 - 最大： | 8GHz |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 管件 |
NB7L14
http://onsemi.com
5
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = 40°C to +85°C ; (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency; VOUT w 400 mV
7
8
GHz
fDATAMAX
Maximum Operating Data Rate; NRZ, (PRBS23)
10
11
Gbps
VOUTPP
Output Voltage Amplitude (Note 15)
fin v 5 GHz
(See Figure 9)
fin ≤ 7 GHz
500
400
720
450
mV
tPLH,
tPHL
Propagation Delay IN to Q
125
165
200
ps
tSKEW
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
3
15
50
ps
tDC
Output Clock Duty Cycle
fin v 7 GHz
(Reference Duty Cycle = 50%)
45
50
55
%
tJITTER
RMS Random Clock Jitter (Note 13)
fin v 7 GHz
PeaktoPeak Data Dependent Jitter (Note 14)
fin v 10.7 Gb/s
0.5
5
0.8
15
ps rms
ps pkpk
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
100
1200
mV
tr
tf
Output Rise/Fall Times @ 1.0 GHz
Qx, Qx
(20% 80%)
30
45
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing VINPP(min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates
40 ps (20% 80%).
12.Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peaktopeak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a singleended measurement operating in differential mode.
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
fin, Clock Input Frequency (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
800
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Q AMP (mV)
Figure 4. Input Structure
50 W
VT
VCC
IN
700
600
500
400
300
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