参数资料
| 型号： | NCN8024RDWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC SMART CARD IC2 28SOIC |
| 标准包装： | 1,000 |
| 系列： | * |
NCN8024R
http://onsemi.com
11
If controlling the clock with RSTIN is not necessary
(Normal Mode), then /CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 500 ns
after the transition on I/O (Figure 5), and to obtain an ATR,
CRST can be set High by RSTIN also about 500 ns after the
clock channel activation (tact).
The internal activation sequence activates the different
channels according to a specific hardware builtit sequencing
internally defined but at the end the actual activation
sequencing is the responsibility of the application software
and can be redefined by the microcontroller to comply with
the different standards and the different ways the standards
manage this activation (for example light differences exist
between the EMV and the ISO7816 standards).
Figure 4. Activation Sequence RSTIN mode (RSTIN Starting High)
CRST
CVCC
CIO
CCLK
CMDVCC
ATR
RSTIN
t0
t1 t2
t4
t5
200 ms
Figure 5. Activation Sequence Normal Mode
CRST
CVCC
CIO
CCLK
CMDVCC
ATR
RSTIN
t0
t1 t2 t3
tact
t4
POWERDOWN
When the communication session is completed the
NCN8024R runs a deactivation sequence by setting High
CMDVCC. The below power down sequence is executed:
CRD_RST is forced to Low
CRD_CLK is set Low 12 ms after CRD_RST.
CRD_IO, CRD_AUX1 and CRD_AUX2 are pulled Low
Finally CRD_VCC supply can be shutoff.
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