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| 型号： | NCP1280DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM PROG OVP HV 16SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 140kHz ~ 320kHz |
| 输入电压： | 7 V ~ 25 V |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 带卷 (TR) |
NCP1280
CCSKIP [
Current Limit
The NCP1280 has two overcurrent protection modes,
cycle by cycle and cycle skip. It allows the NCP1280 to
handle momentary and hard shorts differently for the best
tradeoff in performance and safety. The outputs are disabled
typically 90 ns after a current limit fault is detected.
The cycle by cycle mode terminates the conduction cycle
(reducing the duty cycle) if the voltage on the CS pin
exceeds 0.48 V. If the voltage on the CS pin exceeds 0.57 V,
the converter enters the cycle skip (CSKIP) mode. While in
the CSKIP mode, the soft ? start capacitor is discharged and
the converter is disabled by a time determined by the CSKIP
timer.
The CSKIP timer is set by immediately discharging the
capacitor on the CSKIP pin (C CSKIP ), and then charging it
with a constant current source of 12.3 m A. The cycle skip
period ends when the voltage on the cycle skip capacitor
reaches 2.0 V. The cycle skip capacitor is calculated using
the equation below:
TCSKIP 12.3 m A
2V
Using the above equation, a cycle skip period of 11.0 m s
requires a cycle skip capacitor of 68 pF. The differences
between the cycle by cycle and cycle skip modes are
observed in Figure 32.
V AUX(on)
NORMAL
OPERATION
I LIM1 I L IM2
RESET
SOFT ? START
NORMAL
OPERATION
V AUX
V AUX(off)
0V
OUT2
0V
OUT1
0V
I LIM2
I LIM1
CS Voltage
0V
T CSKIP
Cycle Skip
0V
Voltage
Figure 32. Overcurrent Faults Timing Diagram
Once the cycle skip period is complete and V AUX reaches
11 V, a soft ? start sequence commences. The possible
minimum OFF time is set by C CSKIP . However, the actual
OFF time is generally greater than C CSKIP because it is the
cycle skip period added to the time it takes V AUX to reach
11 V.
Oscillator
The NCP1280 oscillator frequency is set by a single
external resistor connected between the R T pin and GND.
The oscillator is designed to operate up to 500 kHz.
The voltage on the R T pin is laser trim adjusted during
manufacturing to 1.3 V for an R T of 101 k W . A current set
by R T generates an Oscillator Ramp by charging an internal
10 pF capacitor as shown in Figure 2. The period ends
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. If R T increases, the current and the Oscillator Ramp
slope decrease, thus reducing the frequency. If R T decreases,
the opposite effect is obtained. Figure 16 shows the
relationship between R T and the oscillator frequency.
http://onsemi.com
14
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