参数资料
| 型号： | NCP1308DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBACK PWM 8-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 75kHz |
| 电源电压： | 11 V ~ 20 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1308DR2GOSCT |
NCP1308
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 17.
7.0
Figure 19 portrays a typical Vds shot at nominal output
power.
400
300
5.0
3.0
1.0
-1.0
POSSIBLE
RESTARTS
0V
50 mV
200
100
0
Figure 19. The NCP1308 Operates in
Borderline/Critical Operation
Figure 17. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
An internal timer prevents any restart within 10 μ s
further to the driver going-low transition. This prevents the
switching frequency to exceed (1/(T ON + 10 m s)) but also
avoid false leakage inductance tripping at turn-off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The NCP1308 demagnetization detection pad features a
specific component arrangement as detailed by Figure 18.
In this picture, the Zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
Overvoltage Protection
The overvoltage works by monitoring the V CC pin via a
comparator and a reference voltage. Figure 20 portrays the
internal arrangement:
50 us
FILTER
V CC
+
16 V
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with R dem , a restart delay is
created and the possibility to switch right in the
drain-source wave exists. This guarantees QR operation
-
+
OVP
COMPARATOR
with all the associated benefits (low EMI, no turn-on losses
etc.). R dem should be calculated to limit the maximum
current flowing through Pin 1 to less than +3 mA / -2 mA:
if during turn-on, the auxiliary winding delivers -30 V (at
the highest line level), then the minimum R dem value is
defined by: (-30 + 0.7. This value will be further increased
to introduce a restart delay and also a slight filtering in case
of high leakage energy.
TO INTERNAL
TO LATCH
Figure 20. OVP Section Circuitry
A 50 m s time-constant filter prevents any parasitic spikes
superimposed on the V CC to adversely trigger the OVP
comparator. When the OVP comparator output goes high,
the NCP1308 fully latches off and stays latched, being
self-supplied by the DSS. The user must unplug the power
supply and wait that the V CC comes down below a reset
COMPARATOR
R esd
R dem
voltage of typically 4 V.
1
ESD
ESD
Aux
4
Figure 18. Internal Pad Implementation
http://onsemi.com
10
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