参数资料
| 型号： | NCP1308DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBACK PWM 8-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 75kHz |
| 电源电压： | 11 V ~ 20 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1308DR2GOSCT |
NCP1308
Shutting off the NCP1308
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 21. When
OFF, Q1 is transparent to the operation. When forward
biased, the transistor pulls the FB pin to ground (V CEsat ≈
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering
NCP1308
where I DSS is the peak DSS capability, DSS duty- cycle is the
duty-cycle of the DSS, that is to say, the time it is on and
the time it stays off (DSS duty- cycle = on/(on + off) ).
Please refer to the application note AND8069/D
available at www.onsemi.com/pub/ncp1200.
If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary winding
and the V CC pin which will disable the DSS operation
(V CC > 10 V).
1
8
Overload Operation
ON/OFF
10 k
Q1
2
3
7
6
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short-circuit protection.
10 nF
4
5
A short-circuit actually forces the output voltage to be at
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please
Rdrop v bulkmin
t 7.1 k W .
Figure 21. A Simple Bipolar Transistor Totally
Disables the IC
Power Dissipation
The SOIC package offers a 178 ° C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decreasing this number: 12 mm x 12 mm to drop
R θ JA down to 100 ° C/W with 35 m m copper thickness (1 oz)
or 6.5 mm x 6.5 mm with 70 m m copper thickness (2 oz).
As one can see, the designer must be cautious when using
the SO-8 package to check if its thermal performance is
compatible with the total power dissipation. The power
dissipation is simply Vbulk (high line) x I DSS,AVG . The
I DSS,AVG parameter can be measured by inserting an
amp-meter in series with the HV pin and compute its
average value.
We therefore recommend the insertion of a resistor from
the bulk connection to the HV pin. This will help to:
1. Avoid negative spikes at turn-off on the HV pin
(see below)
2. Split the power budget between this resistor and
the package. The resistor is calculated by leaving
at least 50 V on pin 8 at minimum input voltage
(suppose 100 Vdc in our case):
V * 50 V
7.0 mA
The power dissipated by the resistor is thus:
note that this can also happen in case of feedback loss, e.g.
a broken optocoupler. To account for this situation,
NCP1308 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low duty-cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends
on normal output load conditions and the maximum peak
current allowed by the system. The timeout used by this IC
works with the V CC decoupling capacitor: as soon as the
V CC decreases from the VCC OFF level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC ON level is
reached, the controller stops the driving pulses, prevents
the self-supply current source to restart and puts all the
circuitry in standby, consuming as little as 330 m A typical
(ICC3 parameter). As a result, the V CC level slowly
discharges toward 0. When this level crosses 5.3 V typical,
the controller enters a new startup phase by turning the
current source on: V CC rises toward 12 V and again delivers
output pulses at the VCC OFF crossing point. If the fault
condition has been removed before VCC ON approaches,
then the IC continues its normal operation. Otherwise, a
new fault cycle takes place. Figure 22 on the following
page shows the evolution of the signals in presence of a
Pdrop +
+
+
VdropRMS2
Rdrop
(IDSS @ Rdrop @ DSSduty- cycle )2
Rdrop
(7.0 mA @ 7.1 k W @ 0.286) 2
7.1 k W
fault.
+ 99.5 mW
http://onsemi.com
11
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