参数资料
型号: NCP1308DR2G
厂商: ON Semiconductor
文件页数: 8/16页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 8-SOIC
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 75kHz
电源电压: 11 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 剪切带 (CT)
其它名称: NCP1308DR2GOSCT
NCP1308
1 @ Lp @ Ip2 @ F SW @ Dburst with:
The DSS behavior actually depends on the internal IC
consumption and the MOSFET's gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is: FSW @ Qg @ VCC with:
F SW = maximum switching frequency
Qg = MOSFET's gate charge
V CC = V GS level applied to the gate
To obtain the output current, simply divide this result by
V CC : Idriver + FSW @ Qg + 1.6 mA . The total standby
power consumption at no-load will therefore heavily rely
on the internal IC consumption plus the above driving
current (altered by the driver's efficiency). Suppose that
the IC is supplied from a 350 VDC line. The current
flowing through Pin 8 is a direct image of the NCP1308
consumption (neglecting the switching losses of the HV
current source). If I CC2 equals 2.3 mA @ T J = 60 ° C, then
the power dissipated (lost) by the IC is simply:
Skipping Cycle Mode
The NCP1308 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, Pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so-called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 14)
and follows the following formula:
2
Lp = primary inductance
F SW = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D burst = burst width/burst recurrence
350 V x 2.3 mA = 805 mW. For design and reliability
reasons, it would be interesting to reduce this source of
300
MAX PEAK
CURRENT
NORMAL CURRENT
MODE OPERATION
wasted power that increases the die temperature. This can
be achieved by using different methods:
200
SKIP CYCLE
1. Use a MOSFET with lower gate charge Qg
2. Connect a diode to the half-wave portion to
directly supply the HV pin:
100
CURRENT LIMIT
HV
Cbulk
5
1N4007
0
WIDTH
1
2
1
8
6
RECURRENCE
MAINS
2
7
3
4
6
5
Figure 14. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise-Free Operation
DRIVER
DRIVER = HIGH ? I = 0
Figure 13. The Connection to the Half-Wave Signal
Reduces the Dissipated Power on the Controller
RESET
-
+
3
DRIVER = LOW ? I = 200 m A
R skip
3. Permanently force the V CC level above VCC ON
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self-supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit. When the
power supply is switched off, an internal
comparator makes sure that all output pulses are
disable when V CC crosses VCC ON .
R sense
2
+
Figure 15. A Patented Method Allows for Skip
Level Selection via a Series Resistor Inserted in
Series with the Current
http://onsemi.com
8
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