参数资料
| 型号： | NCP1573DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 8-SOIC |
| 产品变化通告： | Product Discontinuation 31/Mar/2005 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 电源电压： | 11.4 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1573DR2OSCT |
NCP1573
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity, particularly at duty cycles above 50%.
Start Up
The NCP1573 features a programmable Soft Start
function, which is implemented through the error amplifier
PWRGD
High
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
Low
V OUT
D VOUT + D IOUT ESL ) ESR ) tTR
voltage overshoot during start ? up. As power is applied to the
regulator, the compensation capacitor connected to the
COMP pin is charged by a 30 μ A current source. When the
capacitor voltage exceeds the 0.525 V offset of the PWM
comparator, the PWM control loop will allow switching to
occur. The upper gate driver GATE(H) is activated, turning
on the upper MOSFET. The current ramps up through the
main inductor and linearly powers the output capacitors and
load. When the regulator output voltage exceeds the COMP
pin voltage minus the 0.525 V PWM comparator offset
threshold and the artificial ramp, the PWM comparator
terminates the initial pulse.
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V 2 control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Input Supplies
The NCP1573 can be used in applications where a 12 V
supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing V GS
available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.
A lower supply voltage between 2 ? 7 V is recommended.
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse ? by ? pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
70% 90%
Percent of
Designed V OUT
Figure 21. PWRGD Assertion
Overvoltage Protection
Overvoltage protection is provided as a result of the
normal operation of the V 2 control method and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Power Good
The PWRGD pin is asserted when the output voltage is
within regulation limits. Sensing for the PWRGD pin is
achieved through the V FB pin. When the output voltage is
rising, PWRGD goes high at 90% of the designed output
voltage. When the output voltage is falling, PWRGD goes
low at 70% of the designed output voltage. PWRGD is an
open ? collector output and should be externally pulled to
logic high through a resistor to limit current to no more than
20 mA. Figure 21 shows the hysteretic nature of the
PWRGD pin’s operation.
CONVERTER DESIGN
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
D t COUT
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