参数资料
| 型号： | NCP1573DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 8-SOIC |
| 产品变化通告： | Product Discontinuation 31/Mar/2005 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 电源电压： | 11.4 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1573DR2OSCT |
NCP1573
V OUT
Layout Considerations
1. The fast response time of V 2 technology increases
the IC’s sensitivity to noise on the V FB line.
Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well, shown below as C6) placed between
V FB and GND, filters out most noise and provides a
system practically immune to jitter. This capacitor
should be located as close as possible to the IC.
2. The COMP capacitor (shown below as C13)
4. The IC should not be placed in the path of
switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.
R4
C6
R6
should be connected via its own path to the IC
ground. The COMP capacitor is sensitive to the
C4
C12
intermittent ground drops caused by switching
currents. A separate ground path will reduce the
potential for jitter.
R3
U1
C13
3. The V CC bypass capacitor (0.1 μ F or greater,
shown below as C4) should be located as close as
possible to the IC. This capacitor ’s connection to
GND must be as short as possible. The 10 Ω
resistor (shown below as R3) should be placed
GND
12 V PWRGD
Figure 26.
R1
5V
close to the V CC pin.
http://onsemi.com
16
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