参数资料
| 型号： | NCP1573DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 8-SOIC |
| 产品变化通告： | Product Discontinuation 31/Mar/2005 |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 电源电压： | 11.4 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1573DR2OSCT |
NCP1573
(VIN * VOUT)(VOUT)
(fOSC)(L)(VIN)
IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE
IRIPPLE +
I I I
2 3 2
where:
D = Duty cycle.
For switching power losses:
PD + nCV2(fOSC)
where:
n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually V CC ),
f OSC = switching frequency.
System Considerations for the NCP1573
The NCP1573 controller is optimized for converter
designs where the power supply for the controller IC has
very short turn ? on and turn ? off times. Such systems can be
found providing power to graphics cards or memory where
standby power is also provided. The key features of the
NCP1573 are that undervoltage lockout and soft start
resetting are not included. These features must be absent to
allow the NCP1573 to interface in a glitch ? free manner with
back ? up power supplies.
A schematic showing a possible system implementation
using the NCP1573 is included in Figure 23. Note that an
external p ? channel FET gates the 12 V supply to the IC. The
signal also controls an alternate supply that drives a linear
regulator. The linear regulator provides back ? up power for
the load during low ? power operation.
In this case, the 12 V supply turn ? on and turn ? off is so fast
that the controller does not charge or discharge the output
capacitance significantly during the transition intervals.
This minimizes glitching during the transitions. Also, note
that a resistor divider and a diode connect the logic signal to
the COMP pin of the NCP1573. The divider and diode
network serve to hold the COMP voltage up when the IC is
powered down. When the power management state changes
and the IC powers back up, having the COMP voltage at its
correct level further reduces glitching. The correct COMP
level is determined to be the IC reference voltage (0.98 V)
plus the channel start ? up offset of the controller (0.525 V),
plus about 10 mV to account for artificial ramp amplitude
(total of 1.615 V). The divider voltage must be about 100 mV
higher to allow for the diode forward voltage. Note that very
little current is assumed to flow through the diode since only
capacitor leakage current should be present.
There will always be some small voltage adjustment
during transitions due to manufacturing tolerances. Having
the COMP voltage slightly low will result in a temporary sag
in the output voltage as the linear regulator turns off and the
switching supply turns on. Similarly, a positive change in
V OUT will occur if the COMP voltage is slightly too high.
PWRGD
R11
10 k
12 V
Q3
GND
5V
3
2
U2
CS5201
V IN
V OUT ADJUST
NTMS10P02R2
Rubycon MBZ
R10
R8
1
C12
L1 2.7 μ H
Q4
R1
R3 47 k
10
Q5
MGSF1N02ELT1
5V
0.01 μ F
1
2
3
4
C4
0.1 μ F
U1
V CC GND
PWRGD V FB
PGDELAY GATEL
COMP GATEH
8
7
6
5
C6
100 pF
C1 + C2 +
1800 μ F 1800 μ F
Q1
MTB1306
SWN
Q2 5.1 k
MTB1306
R6
R4
10 k 1.25 k
R9
1.25 k
NTMS10P02R2
2.5 V
+ C8 + C9
1800 μ F 1800 μ F
C13
0.1 μ F
NCP1573
V FB
LDO_ON_3.3
3.3 k
Rubycon MBZ
Q6
MGSF1N02ELT1
R5
16.9 k
D1
1N5817
R7
16.2 k
Figure 23.
http://onsemi.com
14
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