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| 型号： | NCP1580DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 产品变化通告： | Product Discontinuation 01/Oct/2008 |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 412kHz |
| 占空比： | 95% |
| 电源电压： | 4.5 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP1580
R2 + R1
VREF
VOUT * VREF
w LC +
w ESR +
w P1 +
w P2 +
C1
C2
C1 ) C2
VOUT
R1
FB
R2
Figure 13.
The relationship between the resistor divider network in
Figure 13 and the output voltage is shown in the following
equation:
.
Resistor R1 is selected based on a design trade off between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
The compensation network consists of the internal error
amplifier and the impedance networks Z IN (R1, R3 and C3)
and Z FB (R4, C1 and C2). The compensation network has to
provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response (but always lower
than f SW /8) and the highest gain in DC conditions to
minimize the load regulation. A stable control loop has a
gain crossing with ?20 dB/decade slope and a phase margin
greater than 45 ° . Include worst?case component variations
when determining phase margin. To place the poles and
zeroes of the compensation networks, the following
equations may be used:
Modulator frequencies:
1 1
LOUT COUT ESR COUT
Compensation network frequency:
1 1
R3 C3
R4
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
w Z1 +
R4
1
C2
w Z2 +
1
(R1 ) R3)
C3
following equation (neglecting resistor tolerance):
0.1 m A R1
Error% + 100%
VREF
Once R1 has been determined, R2 can be calculated.
The NCP1580 utilizes voltage mode control. This is to
say, the control loop regulates V OUT by monitoring V OUT
and controlling the output current. However, since the
control loop is controlling the output current to regulate the
output voltage, there are some stability concerns since the
inductor current is 90 degrees out of phase with the voltage.
It is inherent with all voltage?mode control loops to have a
compensation network.
V IN
Place w Z1 , and w Z2 around the output filter resonance
w LC ; Place w P1 at the output capacitor ESR zero w ESR ; Place
w P2 at one half of the switching frequency;
The modulator transfer function is the small?signal
transfer function of V OUT /V COMP . This function has a
double pole at frequency w LC and a zero at w ESR . The DC
Gain of the modulator is simply the input voltage V IN
divided by the peak?to?peak oscillator voltage D V OSC .
Error Amplifier
Closed Loop
Gain
V RAMP
?
+
L OUT
V OUT
ESR
w Z1 w Z2
PWM
COMPARATOR
C OUT
w P1 w P2
C1
R1
w LC
R4
C2
C3 R3
V REF
R2
w ESR
Compensation
Network
Modulator Gain
Figure 15.
Figure 14. Simplified Diagram of Control Loop
Visit http://www.onsemi.com/pub/Collateral/COMPCALC for
self extracting compensation program for design assistance.
http://onsemi.com
9
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