参数资料
型号: NCP1586DR2G
厂商: ON Semiconductor
文件页数: 10/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
产品变化通告: Product Obsolescence 19/Dec/2008
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 300kHz
占空比: 80%
电源电压: 4.5 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
NCP1586
Where:
Q BG = total lower MOSFET gate charge at V CC .
The junction temperature of the control IC can then be
Open Loop, Unloaded Gain
calculated as:
A
Closed Loop,
Unloaded Gain
F Z F P
Gain = GMR 1 B
Compensation Network
Error Amplifier
TJ + TA ) PIC @ q JA.
Where:
T J = the junction temperature of the IC,
T A = the ambient temperature,
θ JA = the junction ? to ? ambient thermal resistance of the
IC package.
The package thermal resistance can be obtained from the
100 1000 10 k 100 k 1000 k
FREQUENCY (Hz)
Figure 10. Gain Plot of the Error Amplifier
Thermal Considerations
The power dissipation of the NCP1586 varies with the
MOSFETs used, V CC , and the boost voltage (V BST ). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
PIC + (ICC @ VCC) ) PTG ) PBG.
Where:
P IC = control IC power dissipation,
I CC = IC measured supply current,
V CC = IC supply voltage,
P TG = top gate driver losses,
P BG = bottom gate driver losses.
The upper (switching) MOSFET gate driver losses are:
PTG + QTG @ fSW @ VBST.
Where:
Q TG = total upper MOSFET gate charge at V BST ,
f SW = the switching frequency,
V BST = the BST pin voltage.
The lower (synchronous) MOSFET gate driver losses are:
PBG + QBG @ fSW @ VCC.
TG
PHASE
V in
specifications section of this data sheet and a calculation can
be made to determine the IC junction temperature. However,
it should be noted that the physical layout of the board, the
proximity of other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the IC,
impact the temperature of the device. Use these calculations
as a guide, but measurements should be taken in the actual
application.
Layout Considerations
As in any high frequency switching converter, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. The figure below shows the critical power
components of the converter. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in the figure below should be
located as close together as possible. Please note that the
capacitors C IN and C OUT each represent numerous physical
capacitors. It is desirable to locate the NCP1586 within 1
inch of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the NCP1586
must be sized to handle up to 2 A peak current.
L out
V out
NCP1586
BG
GND
C in
C out
L
C
A
D
RETURN
Figure 11. Components to be Considered for
Layout Specifications
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