参数资料
型号: NCP1586DR2G
厂商: ON Semiconductor
文件页数: 9/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
产品变化通告: Product Obsolescence 19/Dec/2008
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 300kHz
占空比: 80%
电源电压: 4.5 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
NCP1586
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator ’s maximum achievable
Once R1 has been determined, R2 can be calculated.
LOUT
Ipk * pkLOUT + ,
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak ? to ? peak ripple
current is given by the following equation:
VOUT(1 * D)
275 kHz
where Ipk ? pk LOUT is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
C C
R C
C P
EA
Gm
V REF
+
R1
R2
as L OUT decreases, emphasizing the trade ? off between
dynamic response and ripple current.
Feedback and Compensation
The NCP1586 allows the output of the DC ? DC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V OUT , the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
V OUT
R1
FB
R2
The relationship between the resistor divider network
above and the output voltage is shown in the following
Figure 9. Type II Transconductance Error Amplifier
Figure 9 shows a typical Type II transconductance error
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R 1 , R 2 ) and external Z FB (R c , C c and C p ). The
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than F SW /8) and the highest
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with ? 20 dB/decade
slope and a phase margin greater than 45 ° . Include
worst ? case component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 10. shows the open
loop and closed loop gain plots.
Compensation Network Frequency:
The inductor and capacitor form a double pole at the
frequency
FLC +
equation:
R2 + R1
VREF
VOUT * VREF
.
1
2 p @ LO @ CO
The ESR of the output capacitor creates a “zero” at the
Resistor R1 is selected based on a design tradeoff between
frequency,
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
FESR +
1
2 p @ ESR @ CO
VREF
FZ +
FP +
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
0.1 m A  R1
Error% + 100%.
The zero of the compensation network is formed as,
1
2 p @ RCCC
The pole of the compensation network is calculated as,
1
2 p @ RC @ CP
http://onsemi.com
9
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