参数资料
型号: NCP1586DR2G
厂商: ON Semiconductor
文件页数: 6/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
产品变化通告: Product Obsolescence 19/Dec/2008
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 300kHz
占空比: 80%
电源电压: 4.5 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
NCP1586
DETAILED OPERATING DESCRIPTION
General
The NCP1586 is an 8 ? pin PWM controller intended for
DC ? DC conversion from 5.0 V & 12 V buses. The NCP1586
Vcc
4.0V
BG
has a 1 A internal gate driver circuit designed to drive
N ? channel MOSFETs in a synchronous ? rectifier buck
topology. The output voltage of the converter can be
precisely regulated down to 800 mV ± 1.0% when the V FB
pin is tied to V OUT . The switching frequency, is internally set
to 275 kHz. A high gain operational transconductance error
amplifier (OTA) is used.
Duty Cycle and Maximum Pulse Width Limits
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The NCP1586 can achieve an 80% duty
cycle. There is a built in off ? time which ensures that the
bootstrap supply is charged every cycle. The NCP1586 can
allow a 12 V to 0.8 V conversion at 275 kHz.
Comp
Vfb
550mV
50mV
OCP
Programming
TG
Vout
POR
1.1V
SS
0.8V
Normal
UVLO
IOCth + OCSET
I @ ROCSET
RDS(on)
Input Voltage Range (V CC and BST)
The input voltage range for both V CC and BST is 4.5 V to
13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.4 V with respect to GND.
External Enable/Disable
When the Comp pin voltage falls or is pulled externally
below the 400 mV threshold, it disables the PWM Logic and
the gate drive outputs. In this disabled mode, the operational
transconductance amplifier (EOTA) output source current is
reduced and limited to the Soft ? Start mode of 10 m A.
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.
External Soft ? Start
The NCP1586 features an external soft ? start function,
which reduces inrush current and overshoot of the output
voltage. Soft ? start is achieved by using the internal current
source of 10 m A (typ), which charges the external integrator
capacitor of the transconductance amplifier. Figure 7 is a
typical soft ? start sequence. This sequence begins once V CC
surpasses its UVLO threshold and OCP programming is
complete. During soft ? start, as the Comp Pin rises through
400 mV, the PWM Logic and gate drives are enabled. When
the feedback voltage crosses 800 mV, the EOTA will be
given control to switch to its higher regulation mode output
current of 120 m A.
Figure 7. Soft ? Start Implementation
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V CC is too low to
support the internal rails and power the converter. For the
NCP1586, the UVLO is set to ensure that the IC will start up
when V CC reaches 4.1 V and shutdown when V CC drops
below 3.6 V. This permits operation when converting from
a 5.0 input voltage.
Overcurrent Threshold Setting
NCP1586 allows to easily program an Overcurrent
Threshold ranging from 50 mV to 550 mV, simply by adding
a resistor (RSET) between BG and GND. During a short
period of time following V CC rising over UVLO threshold,
an internal 10 m A current (I OCSET ) is sourced from BG pin,
determining a voltage drop across R OCSET . This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is about 6 ms. Connecting a R OCSET resistor
between BG and GND, the programmed threshold will be:
(eq. 1)
RSET values range from 5 k W to 55 k W . In case R OCSET
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ± 25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
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