参数资料
型号: NCP1586DR2G
厂商: ON Semiconductor
文件页数: 7/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
产品变化通告: Product Obsolescence 19/Dec/2008
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 300kHz
占空比: 80%
电源电压: 4.5 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
NCP1586
Current Limit Protection
In case of a short circuit or overload, the low ? side (LS)
FAULT
1
BST
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The low ? side R DS(on) sense is implemented at
the end of each of the LS ? FET turn ? on duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
+
-
2V
2
8
TG
PHASE
When the counter completes, the PWM logic and both
HS ? FET and LS ? FET are turned off. The controller has to
go through a Power On Reset (POR) cycle to reset the OCP.
+
-
V CC
The minimum turn ? on time of the LS ? FET is set to be 500
nS.
4
BG
Drivers
The NCP1586 includes 1 A gate drivers to switch external
FAULT
3
R set
GND
N ? channel MOSFETs. This allows the NCP1586 to address
high ? power as well as low ? power conversion requirements.
The gate drivers also include adaptive non ? overlap
circuitry. The non ? overlap circuitry increase efficiency,
which minimizes power dissipation, by minimizing the
body diode conduction time.
A detailed block diagram of the non ? overlap and gate
drive circuitry used in the chip is shown in Figure 8.
Figure 8. Block Diagram
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between V CC and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
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