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参数资料
| 型号： | NCP1631PFCGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/23页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO NCP1631 INTERLEAV PFC |
| 设计资源： | NCP1631PFCGEVB BOM NCP1631PFCGEVB Gerber Files NCP1631PFCGEVB Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，功率因数校正 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NCP1631 |
| 已供物品： | 板 |
| 其它名称： | NCP1631PFCGEVBOS |
NCP1631
R out1 ) R out2 ) R out3
V out(nom) + @ V ref
R out2 ) R out3
R out1 ) R out2 ) R out3
V out(ovp) + @ V ref
R out2
V out(ovp) R out3
V out(nom)
R out2
The double feed ? back configuration offers some
up ? graded safety level as it protects the PFC stage even if
there is a failure of one of the two feed ? back arrangements.
However, if wished, one single feed ? back arrangement
is possible as portrayed by Figure 14. The regulation and
OVP blocks having the same reference voltage, the
resistance ratio R out2 over R out3 adjusts the OVP threshold.
More specifically,
The bulk regulation voltage (“V out(nom) ”) is:
(eq. 14)
The OVP level (“V out(ovp) ”) is:
(eq. 15)
The ratio OVP level over regulation level is:
+ 1 ) (eq. 16)
For instance, (V out(nom) = 105% x V out(nom) ) leads to:
(R out3 = 5% x R out2 ).
When the circuit detects that the output voltage exceeds
the OVP level, it maintains the power switch open to stop
the power delivery.
As mentioned previously, the “V TON processing circuit”
is “informed” when there is an OVP condition, not to
over ? dimension V TON in that conditions. Otherwise, an
OVP sequence would be viewed as a dead ? time phase by
the circuit and V TON would inappropriately increase to
compensate it (refer to Figure 7).
PfcOK / REF5V Signal
The NCP1631 can communicate with the downstream
converter. The signal “pfcOK/REF5V” is high (5 V) when
the PFC stage is in normal operation (its output voltage is
stabilized at the nominal level) and low otherwise.
More specifically, “pfcOK/REF5V” is low:
? During the PFC stage start ? up, that is, as long as
the output voltage has not yet stabilized at the
right level. The start ? up phase is detected by
the latch “L STUP ” of the block diagram in
Figure 2. “L STUP ” is set during each “off”
phase so that its output (“STUP“) is high when
the circuit enters an active phase. The latch is
reset when the error amplifier stops charging
its output capacitor, that is, when the output
voltage of the PFC stage has reached its
desired regulation level. At that moment,
“STUP” falls down to indicate the end of the
start ? up phase.
? Any time, the circuit is off or a fault condition is
detected as described by the “Fault
management and OFF mode” section
Finally, “pfcOK/REF5V” is high when the PFC output
voltage is properly and safely regulated. “pfcOK/REF5V”
should be used to allow operation of the downstream
converter.
Oscillator Section – Phase Management
The oscillator generates the clock signal that dictates the
maximum switching frequency for the global system ( f osc ).
In other words, each of the two interleaved branches cannot
operate above the clamp frequency that is half the oscillator
frequency ( f osc /2). The oscillator frequency ( f osc ) is
adjusted by the capacitor applied to pin 4. Typically, a
440 pF capacitor approximately leads to a 120 ? kHz
operating frequency, meaning a 60 ? kHz clamp frequency
for each branch. The oscillator frequency should be kept
below 500 kHz (which corresponds to a pin4 capacitor in
the range of 100 pF ).
As shown by Figure 16, two current sources I OSC(clamp)
(35 m A typical) and I OSC(CH) (105 m A typical) charge the
pin 4 capacitor until its voltage exceeds V OSC(high) (5 V
typically). At that moment, the output of the COMP_OSC
comparator (“SYNC” of Figure 16) turns high and changes
the COMP_OSC reference threshold that drops from
V OSC(high) down to V OSC(low) (hysteresis). The system
enters a discharge phase where the I CH current source is
disabled and instead a sink current I OSC(DISCH) (105 m A
typ.) discharges the pin 4 capacitor. This sequence lasts
until V pin4 goes below V OSC(low) when the “SYNC” signal
turns low and a new charging phase starts. A divider by two
uses the “SYNC” information to manage the phases of the
interleaved PFC: the first SYNC pulse sets “phase 1”, the
second one, “phase 2”, the third one phase 1 again... etc...
According to the selected phase, the “SYNC” signal sets
the relevant “Clock generator latch” that will generate the
clock signal (“CLK1” for phase 1, “CLK2” for phase 2)
when SYNC drops to zero (falling edge detector). So, the
drivers are synchronized to SYNC falling edge.
Actually, the drivers cannot turn on at this very moment
if the demagnetization of the coil is not yet complete (CrM
operation). In this case, the clock signal is maintained high
until the driver turns high (the clock generator latches are
reset by the corresponding driver is high ? reset on rising
edge detector). Also, the discharge time can be prolonged
if when V pin4 drops below V OSC(low) , the driver of the
phase cannot turn on because the core is not reset yet (CrM
operation). In this case, V pin4 decreases until the driver
turns high. The further discharge of V pin4 below V OSC(low)
helps maintain a substantial 180 ° phase shift in CrM that is
in essence, guaranteed in DCM. In the two conditions (CrM
or DCM), operation is stable and robust.
Figure 17 portrays the clock signal waveforms in
different cases:
? In fixed frequency operation (DCM), the cycle
time of the coil current is shorter than an
oscillator period. Hence, as soon as the clock
signal goes high, the driver can turn on and
reset the clock generator latch. The clock
signal is then a short pulse.
http://onsemi.com
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