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参数资料
| 型号： | NCP1631PFCGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/23页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO NCP1631 INTERLEAV PFC |
| 设计资源： | NCP1631PFCGEVB BOM NCP1631PFCGEVB Gerber Files NCP1631PFCGEVB Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，功率因数校正 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NCP1631 |
| 已供物品： | 板 |
| 其它名称： | NCP1631PFCGEVBOS |
NCP1631
60 m R FF (R FF I OSC(clamp) ) 2V REGUL )
f OSC + f OSC(nom)
V REGUL (R FF I OSC(clamp) ) V REGUL )
f OSC +
@ f OSC(nom)
if V REGUL w R FF @ 105 m A
if V REGUL v R FF @ 105 m A
(eq. 20)
R FF +
+ 7.9 k W
105 m A
Let’s illustrate this operation on an example.
V REGUL is the control signal that varies between 0 and
1.66 V, (V REGUL = 1.66 V) corresponding to the maximum
power (P in ) HL that can virtually be delivered by the PFC
stage as selected by the timing resistor (for more details,
you can refer to the application note AND8407).
If one decides to start to reduce the clamp frequency
when the power goes below (P in ) HL /2, the oscillator charge
current should start to decrease when V REGUL is 0.83 V.
Hence, the pin 6 resistor (“R FF ”) must be selected so that
pin 6 sources 105 m A when V REGUL equates 0.83 V:
0.83 V
(eq. 21)
Let’s take (R FF = 8.2 k W ) which is a normalized value.
This selection leads to:
492 m(R FF I OSC(clamp) ) 2V REGUL )
f OSC + f OSC(nom)
V REGUL (R FF I OSC(clamp) ) V REGUL )
f OSC +
if V REGUL w 8.2 k @ 105 m + 860 mV
@ f OSC(nom) if V REGUL v 860 mV
(eq. 22)
For instance, if the nominal frequency (f OSC(nom) ) is 120 kHz, the following characteristic is obtained.
150
100
50
f OSC(nom) = 120 kHz
0
0
0.5
1
1.5
V REGUL (V)
Figure 18. Fold ? back Characteristic of the Clamp Frequency with R FF = 8.2 k W and f OSC(nom) = 120 kHz
If pin6 is grounded (accidently or not), the circuit operates
properly with a constant 140 m A oscillator charge current and
a 105 m A discharge current. The clamp frequency equates its
nominal value over the whole load range.
If pin6 is open, the oscillator charge current is equal to
I OSC(clamp) but the oscillator discharge current is null and
hence the PFC stage cannot operate.
A minimum discharge current and hence a minimum
clamp frequency can be forced by placing a resistor
between pin 4 and ground. For instance, a 1.5 ? M W resistor
forces a 3.3 ? m A discharge current when the oscillator
capacitor is fully charged and about 2.6 m A when it is near
the oscillator low threshold (4 V).
A transistor pulls the pin 6 down during startup to disable
the frequency fold ? back function.
Skip Mode
The circuit features the frequency fold ? back that leads to
a very efficient stand ? by mode. In order to ensure a proper
regulation in no load conditions even if this feature is not
used (pin 6 grounded), the circuit skips cycles when the
error amplifier output is at its minimum level. The error
amplifier output is maintained between about 0.6 V and
3.6 V thanks to active clamps. A skip sequence occurs as
long as the 0.6 V clamp circuitry is triggered and switching
operation is recovered when the clamp is inactive.
http://onsemi.com
18
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