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| 型号： | NCP1650DR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/31页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWR FACTOR PWM 16SOIC |
| 标准包装： | 1 |
| 模式： | 连续导电（CCM），间歇导电（DCM） |
| 频率 - 开关： | 100kHz |
| 电源电压： | 10 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 标准包装 |
| 其它名称： | NCP1650DR2OSDKR |
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NCP1650
OPERATING DESCRIPTION
DC Reference and Buffer
The internal DC reference is a precision bandgap design
with a nominal output voltage of 4.0 volts. It is temperature
compensated, and trimmed for a ± 1% tolerance of its
nominal voltage, with an overall tolerance over line and
temperature of ± 2%. To assure maximum stability, this is
only used as a reference so there is minimal loading on this
source.
The DC reference is fed into a buffer with a gain of 1.625
which creates a 6.5 volt supply. This is used as an internal
voltage to power many of the blocks inside of the NCP1650
by the RC network on the output. This network creates a low
pass filter, and removes the high frequency content from the
original waveform.
INPUT A
V to I
CONVERTER
and is also available for external use. The 6.5 volt reference
is designed to be terminated with at 0.1 m F capacitor for
stability reasons.
INPUT P
RAMP
+
--
There is no buffer between the internal and external 6.5 V
supply, so care should be used when connecting external
Inverting Input
loads. A short or overload on this voltage output will inhibit
the operation of the chip.
There is also a 2.5 volt reference on the power amplifier.
This is derived by a resistive voltage divider off of the 4.0 V
reference.
NI Input
OUTPUT
Undervoltage Lockout
An Undervoltage Lockout circuit (UVLO) is provided to
assure that the unit does not exhibit undesirable behavior at
low Vcc levels. It also reduces power consumption to a level
that allows rapid charging of the Vcc cap.
When the Vcc cap is originally charging, the UVLO will
hold the unit off, and in a low bias current mode until the Vcc
voltage reaches a nominal 10.5 volt level. At this point the
unit will begin operation, and the UVLO will no longer be
active. If the Vcc voltage falls to a level that is 0.5 volts
below the turn--on point, the UVLO circuit will again
become active.
When in the shutdown state, the UVLO circuit removes
power from all internal circuitry by shutting off the 6.5 volt
supply. The 4.0 volt reference remains active, and the UVLO
and Shutdown comparators are also active.
Multipliers
The NCP1650 uses a new proprietary concept for the
Power and Reference multipliers. This innovative design
allows greatly improved accuracy compared to a
conventional linear analog multiplier. The multipliers use a
PWM switching circuit to create a scalable output signal,
with a very well defined gain.
One input (A) to the multiplier is a voltage--to--current
(V--I) converter. By converting the input voltage into a
current, an overall multiplier gain can be accomplished. In
addition, there will be no error in the output signal due to the
series rectifier.
The other signal (Input P) is inputted into the PWM
comparator. This selects a pulse width for the comparator
output. The current signal from the V--I converter is factored
by the duty cycle of the PWM comparator, and then filtered
Figure 34. Simplified Multiplier Schematic
The multiplier ramp is generated by the internal oscillator,
and is the same signal as is used in the PWM. It will therefore
have the same frequency as the power stage.
It is not necessary for Input P (into the PWM comparator)
to be a DC signal, low frequency AC signals (relative to the
ramp frequency) work well also.
The gain of the multiplier is determined by the
current--to--voltage ratio of the V--I converter, the load
resistor of the output filter and the peak and valley points of
the sawtooth ramp. When the P input signal is at the peak of
the ramp waveform, the comparator will allow the A input
signal to pass without chopping it at all. This gives an output
voltage of the A current multiplied by the output filter
resistance. When the P input signal is at the ramp valley
voltage, the comparator is held low and no current is passed
into the output filter. Between these two extremes, the duty
cycle (and therefore, the output signal) is proportional to the
level of the P input signal.
The output filter is a parallel RC network. The pole for this
network needs to be greater than twice the highest line
frequency (120 Hz for a 60 Hz line), and less than the
switching frequency.
Reference Multiplier The two multipliers have different
rules for designing their filters. The reference multiplier
contains an internal loading resistor, with a nominal value of
25 k Ω . This is because the resistor that converts the A input
voltage into a current is internal. Making both of these
resistors internal, allows for good accuracy and good
temperature performance. Only a capacitor needs to added
externally to properly compensate this multiplier. It is not
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