参数资料
| 型号： | NCP4326DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/29页 |
| 文件大小： | 0K |
| 描述： | IC SECONDARY CTLR SW PS 16-SOIC |
| 产品变化通告： | Discontinuation 30/Jun/2006 |
| 标准包装： | 2,500 |
| 应用： | 次级控制器，准谐振切换模式电源 |
| 输入电压： | 15V |
| 输出数： | 3 |
| 工作温度： | 0°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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NCP4326
Flux Image Reconstruction
With a primary controller working in critical conduction
mode the core flux inside the transformer is null at each
beginning primary switching cycle.
Measuring the flux means integrating the voltage present
on a transformer winding. But a simple integration yields a
saw tooth voltage waveform centered to zero volts. Thus this
saw tooth represents the flux variation in the transformer
core and must be offset in order to have a true image of the
flux with a minimum voltage close to zero volts.
What we need is a triangle with a FIXED lower level,
being equal to or somewhat above zero. This necessitates the
resetting of the integrator at the beginning of each primary
on ? time. In practice, it means we quickly discharge the
integrator capacitor just before the primary on ? time and
release this capacitor at the start of the primary on ? time.
A negative auxiliary winding or a forward winding can be
used to build the flux image via a simple RC network, which
it ensures the integration then the NCP4326 fixes the lower
level.
Figure 46 shows how the flux image is built and used for
the soft ? start sequence.
The RC network (Rint & Cint) connected to the negative
output winding does the integration of the voltage present on
this winding that it yields the flux image. Then the voltage
available on Flux pin is clamped between a low and high
level (respectively V Flux_L and V Flux_H ) in order to ensure
a positive saw tooth on Flux pin. After that the voltage on
Flux pin is amplified 10 times and an offset is inserted to
ensure the disable function when the enable pin is below
V ENX_TH1 . More over the internal voltage clamp
(V ENX_TH2 = 4.5 V) ending the soft ? start duty cycle
generation when the voltage on enable pin is between
V ENX_TH2 and V ENX_max1 .
Next the internal Flux image (label Int_Flux on Figure 46)
is compared with the enable pin voltage for generating the
soft ? start duty cycle in leading edge mode control.
On enable pin we have an internal current source that it
charge the external capacitor and fix the soft ? start time by
playing with the capacitor value. If the controller is placed
in standby mode then the enable capacitor is discharged by
the internal switch. The internal clamp limits the voltage
range on the enable pin.
D1
Q1
HV Rail
T1
+
Pos Out
C1
GND
Primary
Controller
Q2
D2
+
C2
Neg Out
GND
Rint
Cint
Flux
Clamp
1V 0V
+
?
Offset
0V5
Int_Flux
4V5
?
+
PWM_SS
DRVx
GND
GND
R
V DD
9R
GND
Normal_Reg
PWM_REG
IENx
ENx_CMD
ENx
+
C_SS
GND GND
V DD
5V0
GND GND
Soft ? Start Secondary Controller
Figure 46. Soft ? Start Detailed Schematic View
http://onsemi.com
23
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