参数资料
| 型号： | NCP4326DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/29页 |
| 文件大小： | 0K |
| 描述： | IC SECONDARY CTLR SW PS 16-SOIC |
| 产品变化通告： | Discontinuation 30/Jun/2006 |
| 标准包装： | 2,500 |
| 应用： | 次级控制器，准谐振切换模式电源 |
| 输入电压： | 15V |
| 输出数： | 3 |
| 工作温度： | 0°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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NCP4326
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = 0 ° C to +105 ° C, Vcc = 12 V unless
otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Flux Pin
Internal Current Sourced by Flux pin when it is grounded (Note 5)
Maximum Sink Current on Flux pin when the internal 1.0 V clamp is
activated
14
14
I Flux
I Flux_max
?
?
120
?
?
1.0
m A
mA
Input Clamp Voltage
14
High state: when a current is sunk by pin 14 (Ipin 14 = I Flux_max )
Low state: when a current is sourced by pin 14 (Ipin 14 = ? 1.0 mA)
V Flux_H
V Flux_L
?
?
1.4
? 60
?
?
V
mV
Internal Voltage gain of input signal sensed on Flux pin
14
Gain
?
9.5
?
N/A
(guaranteed by design)
Synchronization Block
Input Threshold Voltage (Vpin 7 decreasing)
Hysteresis (Vpin 7 increasing)
Maximum Sink Current on Sync pin when the internal 7.0 V clamp is
activated
Input Clamp Voltage
High state: when a current is sunk by pin 7 (Ipin 7 = I sync_max )
Low state: when a current is sourced by pin 7 (Ipin 7 = ? 3.0 mA)
Delay between the Sync and DRVx pin (Figures 8 and 9), when
applying a falling edge on Sync in normal mode operation (Note 6)
with 1.0 nF connected to DRVx pin
Delay between the Ct voltage (V Ct ) and DRVx pin (Figures 8 and 9),
when applying a rising edge on Ct @ V CPx = 1.7 V in normal mode
operation (Note 6) with 1.0 nF connected to DRVx pin
Internal input capacitance at Vpin 7 = 1.0 V
7
7
7
7
7
7 and 11
or
7 and 13
4, 7 and 11
or
1, 7 and 13
7
V sync _ th
V sync_Hyst
Is ync_max
VC H
VC L
T prop_ON
T prop_OFF
C par
50
?
?
?
?
?
?
?
70
35
?
7.4
? 0.3
200
280
10
100
?
3.0
?
?
500
500
?
mV
mV
mA
V
ns
ns
pF
Error Amplifier Section 1 and 2
Voltage Feedback Input @ T J = 25 ° C (Note 7)
2, 5
V FB1, 2
1.241
1.253
1.266
V
* Voltage follower measurement to reach 1% accuracy
Input Bias Current (V FB = 1.30 V)
Open Loop Voltage Gain (V CPx = 1.0 V to 5.0 V)
Unity Gain Bandwidth (T J = 25 ° C)
Power Supply Rejection Ratio
(Vcc = 10 V to 15 V, Frequency range 120 Hz)
Output Current
Sink Current (V CPx = 1.1 V, V FB = 1.45 V)
Source Current (V CPx = 4.5 V, V FB = 1.05 V)
Output Voltage Swing
High State (R L = 15 k to Ground, V FB =1.05 V)
Low State (R L = 15 k to Vcc, V FB =1.45 V)
2, 5
2, 5
2, 5
2, 5
1, 4
1, 4
1, 4
1, 4
I IB1, 2
A VOL1, 2
BW 1, 2
PSRR 1, 2
I sink1, 2
I source1, 2
V OH1, 2
V OL1, 2
?
?
?
?
2.0
?
4.8
?
? 0.1
90
3.3
55
+6.0
? 13
5.0
0.7
?
?
?
?
?
? 5.0
?
1.1
m A
dB
MHz
dB
mA
V
5. See characterization curves I Flux_pin (V Flux_pin ) with ? 100 mV < V Flux_pin < +100 mV.
6. Normal operation when V ENX > V ENX_TH3 .
7. See characterization curve for Voltage Reference vs. Temperature.
http://onsemi.com
8
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