参数资料
| 型号： | NCP4326DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/29页 |
| 文件大小： | 0K |
| 描述： | IC SECONDARY CTLR SW PS 16-SOIC |
| 产品变化通告： | Discontinuation 30/Jun/2006 |
| 标准包装： | 2,500 |
| 应用： | 次级控制器，准谐振切换模式电源 |
| 输入电压： | 15V |
| 输出数： | 3 |
| 工作温度： | 0°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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NCP4326
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
Symbol
CP1
FB1
EN2
Type
Error Amplifier
Output 1
Voltage
Feedback 1
Soft ? Start and
Enable or Disable
the Driver 2
Description
This pin is the output of the error amplifier 1 (monitoring the secondary voltage #1) and is
available for loop compensation purpose.
This is the inverting input of the error amplifier 1. It is connected to the secondary voltage
#1 via a bridge resistor divider.
This pin enables or disables the driver 2. An internal current source with an external
capacitor generates also a soft ? start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 2, but without soft ? start
feature.
4
5
6
7
8
9
10
11
12
13
14
15
16
CP2
FB2
Ct
Sync
CPm
FBm
STBY
DRV2
Vcc
DRV1
Flux
GND
EN1
Error Amplifier
Output 2
Voltage
Feedback 2
Ct Pin
Synchronization
Pin
Shunt Regulator
Output
Main Voltage
Feedback
Standby
Output Driver 2
Supplies the IC
Output Driver 1
Voltage image of
the magnetic flux
The IC ground
Soft ? Start and
Enable or Disable
the driver 1
This pin is the output of the error amplifier 2 (monitoring the secondary voltage #2) and is
available for loop compensation purpose.
This is the inverting input of the error amplifier. It is connected to the secondary voltage #2
via a bridge resistor divider.
Connect the timing capacitor between Ct and the ground.
This pin monitors the main secondary winding, detects the beginning and the end of the
demagnetization phase (T OFF time on the primary winding) and allows the regulation on
the two secondary outputs.
This pin is the output of the shunt regulator (monitoring the main secondary voltage). An
open collector configuration is implemented.
This is the inverting input of the internal error amplifier. It is connected to the main output
voltage via a bridge resistor divider.
This pin is internally pulled up and allows standby mode feature. This pin can be left open
and by default it enables standard working mode. When this pin is pulled down standby
mode is activated and the quiescent current is reduced to the minimum. The output drivers
are disabled.
This output directly drives the gate of a power MOSFET.
This pin is connected to the main secondary output voltage and internally powers the IC.
This output directly drives the gate of a power MOSFET.
A RC network connected between this pin and a forward winding or a negative output
winding generates the transformer ’s flux image. This flux image is compared to a slow
ramp generated on ENx pin for the soft ? start Duty Cycle generation controlling the both
outputs.
?
This pin enables or disables the driver 1. An internal current source with an external
capacitor generates also a soft ? start feature for limiting the startup peak current on the
controlled output.
This pin can be left open and by default it enables the driver 1, but without soft ? start
feature.
http://onsemi.com
4
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