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参数资料
| 型号： | NCP4331DBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-TSSOP |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 最高 30V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
NCP4331
Generally speaking the pin voltage is clamped to be between
-100 mV and 10 V. It is recommended to apply the
synchronization signal (“V in ” typically) through a resistor
so that the current absorbed and sourced by the pin clamp
network stays in the range of 1 mA.
Bootstrap Pin
The circuit features a bootstrap pin (“BST”) to optimally
drive the high-side N-MOSFET. A 0.1 m F to 1 m F ceramic
capacitor should be connected between this pin and the 'HB”
node that is connected to the source of the high-side
MOSFET. The “BST” voltage feeds the high-side driver
(“HS_DRV”). Practically, the V DD voltage is applied to the
“BST” pin through a diode (see application schematic of
page 1) so that the bootstrap capacitor is charged to V DD
when the “HB” pin is low (when the low-side MOSFET
conducts). Hence, some voltage source referenced to the
“HB” node (and then to the high-side MOSFET source) is
made available for an effective control of the high-side
MOSFET.
Internal Voltage Regulator
The circuit incorporates a voltage regulator to ease the
circuit feeding. Pin 16 makes the input of this regulator
available. It can receive a dc voltage (up to 30 V). This
voltage is post-regulated down to 9 V to provide the V DD
voltage that supplies the circuit .
Undervoltage Lockout (UVLO)
An under-voltage lockout comparator is incorporated to
guarantee that the device is properly supplied before
enabling the output stages. The NCP4331 starts to operate
when the power supply V DD exceeds 6.0 V. A 0.4 V
hysteresis avoids erratic turning on and off of the device.
Also, a post-regulator having to operate in a noisy
environment, a 30 m s blanking time avoids that an UVLO is
detected because of a spike or of some noise. When the
NCP4331 detects an under-voltage lockout condition, the
“fault” flag is asserted and both the high-side and low-side
drivers are forced off.
A minimum V CC voltage must be present (at least 3 V) to
ensure the active grounding of the drivers. If V CC is lower,
the drivers may be only tied to ground by a 60 k W internal
resistor
The undervoltage lockout has a 5 V minimum threshold
(falling). As a consequence, 5 V minimum are available to
drive the power switch. Such a level generally allows an
efficient drive of most MOSFETs.
Undervoltage Protection (UVP)
This pin is designed to receive a low inertia voltage
representative of the input voltage magnitude, in order
detect too low input voltage pulses and to turn off both the
low-side and high-side drivers in such a faulty condition.
The soft-start pin is grounded when an UVP condition is
detected so that the circuit smoothly recovers operation
when the fault disappears. In addition to the permanent
60 mV hysteresis of the UVP comparator, this block sources
25 m A out of pin4 when no UVP is detected, to further
increase the hysteresis as much as necessary to avoid erratic
turns on and off of the device.
A 5 m s blanking time avoids inappropriate UVP detection
that may result from the application noise.
Thermal Shutdown (TSD)
The NCP4331 senses its junction temperature. When it
exceeds 150 ° C, the circuit turns low both the high-side and
low-side drivers. The power switches are kept off until the
temperature has dropped to about 100 ° C (50 ° C hysteresis).
Like the Undervoltage Lockout block, the TSD incorporates
a 30 m s blanking time to avoid any false detection that may
result from noise.
http://onsemi.com
16
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