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| 型号： | NCP4331DBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-TSSOP |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 最高 30V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
NCP4331
MAXIMUM RATINGS
Symbol
BST, HB
BST HB
V CC
V in
V DD
R q JA
T A
T Jmax
T Smax
Rating
Bootstrap and “Half-Bridge” Node Inputs (Referenced to GND)
Bootstrap Pin Voltage Referenced to the HB Node
Internal Regulator Input
Pins 1, 2, 3, 4, 5, 6, 7, 8 and 9
Supply Voltage
Thermal Resistance (TSSOP-16 and SOIC-16)
ESD Capability, Human Body Model (HBM)
ESD Capability, Machine Model (MM) (Note 2)
Operating Temperature Range (Note 1)
Maximum Junction Temperature
Storage Temperature Range
Value
-2, +40
-0.3, +10
-0.3, +30
-0.3, +5
-0.3, +10
145
2
200
-40, +125
150
-65 to 150
Unit
V
V
V
V
V
° C/W
kV
V
° C
° C
° C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum junction temperature should not be exceeded.
2. The Machine Model ESD capability is 150 V for Pin 9.
ELECTRICAL CHARACTERISTICS (V CC = 20 V, V BST = 7 V, HB Grounded, T J = 0 ° C to +125 ° C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
HIGH-SIDE OUTPUT STAGE
R HS_source
R HS_sink
Source Resistance @ I source = 100 mA
Sink Resistance @ I sink = 100 mA
-
-
3
2
6
4
W
W
Rise and Fall Times:
ns
t r-HS
t f-HS
High-Side Output Voltage Rise Time (C L = 1 nF) (Note 3)
High-Side Output Voltage Fall Time (C L = 1 nF) (Note 3)
-
-
13
8
20
15
T LS-HS
Delay from Low-Side Gate Drive Low (High) to High-Side Drive High
35
55
75
ns
(Low) (Note 6)
LOW-SIDE OUTPUT STAGE
R LS_source
R LS_sink
Source Resistance @ I source = 100 mA
Sink Resistance @ I sink = 100 mA
-
-
3
2
6
4
W
W
Rise and Fall Times:
ns
t r-LS
t f-LS
High-Side Output Voltage Rise Time (C L = 1 nF) (Note 3)
High-Side Output Voltage Fall Time (C L = 1 nF) (Note 3)
-
-
13
8
20
15
CURRENT CONTROL ERROR AMPLIFIER (Auxiliary Error Amplifier)
IB pin3
IB pin2
V io
BW
G EA
V LL
Noninverting Input Bias Current @ V pin3 = V pin2 = V ref
Inverting Input Bias Current @ V pin3 = V pin2 = V ref
Input Offset Voltage (Note 5)
Gain Bandwidth
Open Loop Voltage Gain
Pin 1 Voltage if V pin2 = 1 V and V pin3 = 0 V, 100 m A Being Sourced Into
-500
-500
-5
-
-
0
-100
-100
1
4
70
-
0
0
5
-
-
0.5
nA
nA
mV
MHz
dB
V
Pin 1
3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive
to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design.
4. Guaranteed by design. Tested through the R RESET parameter.
5. Guaranteed by characterization and design.
6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically
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