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| 型号： | NCP5424DG |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 21/Jan/2010 |
| 标准包装： | 48 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
NCP5424
allow a short PWM pulse. This pulse will gradually increase
in width as the voltage ramp on the Compensation Capacitor
continues to rise. This process will continue until the output
voltage reaches the designed value set by the feed back
resistors and the parts 1.0?volt reference voltage. Thus the
user can determine both Soft?Start and power sequence
the buildup of negative currents that arise during a long start
interval where the bottom FET of controller 2 is on. For
applications where there are two outputs, this problem can
not occur.
V IN
functions by selecting the compensation capacitors and
simply knowing that the amplifiers charge these capacitors
with 30 uA and that the threshold for starting PWM pulses
is 0.45 volts.
COMP2
(V IN ? 1.15)
0.958
k W
8.6 V
V IN
Comp
Cap
1.2 k W
V COMP
t S
0.45 V
UVLO
STARTUP NORMAL OPERATION
Figure 4. Idealized Waveforms
V FB
GATE(H)1
GATE(H)2
Figure 5. Preventing Reverse Current
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V 2 control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load
conditions will result in changes in duty cycle to maintain
regulation.
90
80
70
60
50
40
Average Fall Time
Average Rise Time
30
Zero Current Start Up in Single Output Shared Input
20
Current Applications
One problem that occurs with dual controllers when
connected as a single output is that reverse currents can
10
0
0
1
2
3
4
5
6
7
8
occur during zero load conditions. As the two controllers
start up and start delivering current, if there is no load a
reverse current will develop in the inductor of controller 2
that is equal and opposite the current in the controller 1
inductor. When the controller 2 starts to deliver power this
reverse current will flow backwards through the top FET
back into the supply. In the extreme this can cause the supply
to over voltage and/or shut down. Fortunately, there are
several ways to deal with this problem. One is to simply
insure the part has a minimum load. Another is illustrated in
Figure 5, where a diode and voltage divider biases the
controller 2 Compensation Capacitor above the 0.45 V
Soft?Start threshold, such that the controller starts switching
Load (nF)
Figure 6. Average Rise and Fall Times
Transient Response
The 150 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse?by?pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
without a soft?start delay. The effect of this is to eliminate
http://onsemi.com
8
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