参数资料
| 型号： | NCV7608DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC DVR LO/HI SIDE 8CH 28-SOIC |
| 标准包装： | 1,000 |
| 类型： | 高端/低端，H 桥 |
| 输入类型： | SPI |
| 输出数： | 8 |
| 导通状态电阻： | 1.2 欧姆 |
| 电流 - 峰值输出： | 350mA |
| 电源电压： | 3.15 V ~ 5.25，5.5 V ~ 28 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
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NCV7608
SPI Input
Driver Enable (bits 0 ? 7)
A zero turns the driver off.
A one turns the driver on.
Open Load Diagnostic (bits 8 ? 15)
A zero programming bit disables the detection of an open
Parallel Input (INx) State (bits 9 ? 12)
The state of the parallel (PWM) input pins (Inx) are
mirrored to SPI output bits #9 ? 12. When overcurrent or
thermal shutdown fault occurs, bits 9 through 12 record the
state of INx. This enables the user to distinguish an open load
fault from an over current fault when the NCV7608 is
operated from two isolated controllers for the SPI input and
the Parallel input.
load condition.
A one programming bit enables the detection of an open load
condition.
SPI Output
Table 3. SO DRIVER STATUS INFORMATION SUMMARY (Bits 0 ? 8, 15)
Driver
Enable
Disabled
Disabled
Enabled
Open Load
Diagnostic
enable
Disabled
Enabled
X
SO Feedback
0
0 (No Open Load)
1 (Open Load Detected)
0 (No Fault)
1 (Over Current)
1 (VS Power supply fail)
1 (Thermal Warning)
1 (Thermal Shutdown)
Status Information Reset Requirement
N/A
N/A
N/A
N/A
A valid SPI command with the offending Driver DISABLED is re-
ceived.
Any valid SPI command AND VS within limits
N/A
The over temperature goes away AND a valid SPI frame with the
offending driver pair DISABLED is received.
X=Don’t Care
Frame Detection
Input word integrity (SI) is evaluated by the use of a frame
consistency check. The word frame length is compared to an
n * 16 bit (where n is an integer) acceptable word length
before the data is latched into the input register. This
guarantees the proper word length has been imported and
allows for daisy chain operation applications.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
CSB
SCLK
The frame length detector is enabled with the CSB falling
edge and the SCLK rising edge.
SCLK must be low during the CSB rising edge.
Reference the valid SPI frame shown below.
Frame detection mode ends with
CSB rising edge.
SI
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OL1
OL2
OL3
OL4
OL5
OL6
OL7
OL8
Internal Counter 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Valid 16 bits shown
16
Figure 25. Frame Detection
PWM Operation
Channels 5, 6, 7, and 8 can be controlled via the serial port
(SPI) or via the respective parallel port input pins
(IN5 ? IN8).
The SPI information is OR’d with the respective Parallel
input control pins (INx).
INx = 1 activates the output stage.
http://onsemi.com
16
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