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参数资料
型号： NCV8855BMNR2GEVB
厂商： ON Semiconductor
文件页数： 10/24页
文件大小： 0K
描述： BOARD EVALUATION NCV8855 ASIC
设计资源： NCV8855BMNR2GEVB Schematic
NCV8855 BOM
标准包装： 1
主要目的： DC/DC，LDO 步降
输出及类型： 4，非隔离
电流 - 输出： 2.5A
输入电压： 9 V ~ 18 V
稳压器拓扑结构： 降压
频率 - 开关： 170kHz
板类型： 完全填充
已供物品： 板
已用 IC / 零件： NCV8855
其它名称： NCV8855BMNR2GEVBOS
NCV8855
ELECTRICAL CHARACTERISTICS (V IN_SW = V IN = V ISNS1+ = V ISNS1 ? = V ISNS2+ = V ISNS2 ? = 13.2 V, SYS_EN = LDO_EN =
HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range ? 40 ° C v T J v
150 ° C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS
Current Limit
ISNS1+ leakage current
ISNS1 ? leakage current
I ISNS1+
I ISNS1 ?
SYS_EN = 0, T J = 25 ° C, V ISNS1+ = 13.2 V
SYS_EN = 0, T J = 25 ° C, V ISNS1 ? = 13.2 V
100
100
500
500
nA
nA
Short circuit threshold voltage
Short circuit blanking time
V LR_FB1 % of V REF
From rising edge of LDO_EN
60
10
70
12
80
14
%
ms
Error Amplifier
Feedback bias current
LR_FB1 = 0.5 V
100
500
nA
Maximum |V GS |
2 mA, internally clamped
10
11.7
13.5
V
LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO2, VOUT4) SPECIFICATIONS
Output Voltage Regulation
Output voltage accuracy
V LR_FB2 tied to VOUT4 directly,
NTD20P06L pass device
? 2
2
%
Output voltage line regulation
Output voltage load regulation
IOUT4 = 10 mA, 9 V v V ISNS2+ v 18 V,
NTD20P06L pass device
1 mA v IOUT4 v 500 mA, NTD20P06L
pass device
? 0.25
? 0.5
0.01
0.2
0.25
0.5
%
%
Output load capacitance range
Output load capacitance ESR range
Power supply ripple rejection
C OUT4
PSRR2
(Note 1)
(Note 1)
NTD20P06L pass device (Note 1)
10
0.01
60
100
5
m F
W
dB
Current Limit
Current limit threshold voltage
ISNS2+ leakage current
ISNS2 ? leakage current
Short circuit threshold voltage
Short circuit blanking time
V SNS2
I ISNS2+
I ISNS2 ?
V ISNS2+ – V ISNS2 ?
SYS_EN = 0, T J = 25 ° C, V ISNS2+ = 13.2 V
SYS_EN = 0, T J = 25 ° C, V ISNS2 ? = 13.2 V
V LR_FB2 % of V REF
From rising edge of LDO_EN
90
60
10
110
100
100
70
12
130
500
500
80
14
mV
nA
nA
%
ms
Error Amplifier
Feedback bias current
LR_FB2 = 0.5 V
100
500
nA
Maximum |V GS |
2 mA, internally clamped
10
11.7
13.5
V
High ? side Load Switch (HSS)
Current Limit
Peak current limit
Short circuit timeout
Short circuit threshold voltage
I HSSLIM
t SCP
V SCP(HS_S)
2.00
1.300
4.0
2.80
1.506
4.5
3.64
1.800
5.0
A
ms
V
Current overload threshold voltage
Current overload timeout
V DS
V IN – V HS_S
3.3
2.600
3.95
3.012
4.6
3.600
V
ms
Voltage Clamp
Source output positive clamping voltage
Source output negative clamping voltage
V CLAMP+
V CLAMP ?
1 mA v I HS_S v 2 A
V CLAMP+ v V IN v V OVP
I LOADSW = 50 mA
15.4
? 1.6
16.0
16.6
V
V
1. Guaranteed by design, not fully tested in production.
2. Indirectly guaranteed by test coverage of other parameters.
http://onsemi.com
10
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