参数资料
| 型号： | NCV890231MWTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 10-DFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-DFN（3x3） |
| 其它名称： | NCV890231MWTXGOSDKR |
NCV890231
SYNCHRONIZATION
Two NCV890231 can be synchronized out ? of ? phase to
one another by connecting the SYNCO pin of one to the
SYNCI pin of the other (Figure 29). Any number of
NCV890231 can also be synchronized to an external clock
(Figure 30). If a part does not have its switching frequency
controlled by the SYNCI input, it drives the SYNCO pin low
when it turns on the power switch, and drives it high half a
switching period later. When the switching frequency is
controlled by the SYNCI input, the SYNCO pin is held low.
Synchronization starts within 2 ms of soft ? start completion.
A rising edge at the SYNCI pin causes an NCV890231 to
immediately turn on the power switch. If another rising edge
VIN
does not arrive at the SYNCI pin within the Master
Reassertion Time, the NCV890231 controls its own
switching frequency, allowing uninterrupted operation in
the event that the clock (or controlling NCV890231) is
turned off.
If internal conditions or excessive input voltage cause an
NCV890231 to fold back its switching frequency, the main
oscillator switching frequency is still derived from the
frequency received at the SYNCI pin. Under these
conditions, the SYNCO pin is held low.
An external pulldown resistor is not required at the
SYNCI pin if it is unconnected.
CDRV1
CDRV2
NCV890231
DBST1
CIN2
NCV890231
1 VIN SW 1 0
2 DRV BST 9
DBST2
CBST2
L2
DFW2
RFB1
VOUT2
COUT2
CIN1
1 VIN
2 DRV
3 SYNCO
SW 1 0
1
CBST
BST 9
SYNCI 8
L1
DFW1
RFB1
VOUT1
COUT1
3 SYNCO
SYNCI 8
Synchronization
4 GND
FB 7
4 GND
FB 7
5 EN
COMP 6
RFB2
EN2
5 EN
COMP 6
RFB2
SYNC MASTER
RCOMP1
RCOMP2
CCOMP1
SYNC SLAVE
CCOMP2
Figure 29. NCV890231s Synchronized to Each Other
Master Enabled by Battery
VIN
CDRV1
2
CDRV
NCV890231
DBST1
CIN2
NCV890231
1 VIN SW 1 0
DBST2
CBST2
L2
VOUT2
CIN1
1 VIN
2 DRV
SW 1 0
1
CBST
BST 9
DFW1
L1
VOUT1
COUT1
2 DRV
BST 9
DFW2 RFB21
COUT2
3 SYNCO
SYNCI 8
RFB11
3 SYNCO
SYNCI 8
4 GND
FB 7
4 GND
FB 7
5 EN
COMP 6
RFB12
EN2
5 EN
COMP 6
RFB22
RCOMP2
Synchronization
RCOMP1
CCOMP1
CCOMP2
CLK
Figure 30. Both NCV890231s Synchronized to External Clock
#1 Enabled by Battery
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