参数资料
| 型号： | NCV890231MWTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 10-DFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-DFN（3x3） |
| 其它名称： | NCV890231MWTXGOSDKR |
NCV890231
BOOTSTRAP
7
At the DRV pin an internal regulator provides a
ground ? referenced voltage to an external capacitor (C DRV ),
to allow fast recharge of the external bootstrap capacitor
(C BST ) used to supply power to the power switch gate driver.
If the voltage at the DRV pin goes below the DRV UVLO
Threshold V DRVSTP , switching is inhibited and the
Soft ? start circuit is reset, until the DRV pin voltage goes
back up above V DRVSTT .
In order for the bootstrap capacitor to stay charged, the
6
5
4
3
2
V OUT = 5 V
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890231 skips switching
cycles to ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
1
0
0
0.2
0.4
0.6
0.8 1.0
I OUT (A)
1.2
1.4
1.6
1.8 2.0
Practically, this means that the NCV890231 needs a
minimum load to operate correctly: to cover all conditions
of input voltage and temperature, this minimum load is 8
mA.
OUTPUT PRECHARGE DETECTION
Prior to Soft ? start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
bootstrap capacitor (C BST ). If the FB pin is higher than
V SSEN , restart is delayed until the output has discharged.
THERMAL SHUTDOWN
A thermal shutdown circuit inhibits switching, resets the
Soft ? start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
Figure 31. Minimum Input Voltage vs. Output Current
EXPOSED PAD
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise ? free operation.
DESIGN METHODOLOGY
The NCV890231 being a fixed ? frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 m H, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode.
Output capacitor:
The minimum output capacitor value can be calculated
8 @ D V OUT @ F SW
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
based on the specification for output voltage ripple:
D I L
C OUT min +
With
(eq. 1)
OUT
V OUT @ 1 * V
L @ F SW
R ESR max +
V (eq. 3)
V OUT 1 *
IN
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890231 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (t OFFmin ) to periodically re ? fuel
the bootstrap capacitor C BST . This imposes a maximum duty
ratio D MAX = 1 ? t OFFmin .F SW(min) , with the switching
frequency being folded back down to F SW(min) = 500 kHz to
keep regulating at the lowest input voltage possible.
The drop due to the on ? state resistance is simply the
voltage drop across the Switch resistance R DSON at the
given output current: V SWdrop = I OUT .R DSon .
Which leads to the maximum output voltage in low Vin
condition: V OUT = D MAX .V IN(min) ? V SWdrop
? D I L the inductor ripple current:
V
IN (eq. 2)
D I L +
? D V OUT the desired voltage ripple.
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed R ESRmax :
D V OUT @ L @ F SW
OUT
V
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13
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