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| 型号： | NOII5SM1300A-QDC |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/33页 |
| 文件大小： | 0K |
| 描述： | SENSOR IMAGE MONO CMOS 84-LCC |
| 标准包装： | 1 |
| 象素大小： | 6.7µm x 6.7µm |
| 有源象素阵列： | 1280H x 1024V |
| 每秒帧数： | 27 |
| 电源电压： | 3 V ~ 4.5 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 84-LCC |
| 供应商设备封装： | 84-LCC（18x18） |
| 包装： | 托盘 |
| 请注意： | * |
| 其它名称： | CYII5SM1300AB-QDC CYII5SM1300AB-QDC-ND |
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NOII5SM1300A
X ? Addressing
Because of the high pixel rate, the X-shift register selects
two columns at a time for readout, so it runs at half the
system clock speed. All even columns are connected to
Y_SYNC Y_SUB
Y_SWAP12 Y_SWAP30
Reg(n)
bus A; all odd columns to bus B. In the output amplifier,
bus A and bus B are combined into one stream of pixel data
at system clock speed.
At the end of the row blanking time, the X_SYNC switch
is closed while all other switches are open and the decoder
output is fed to the register. The decoder loads a logical one
in one of the registers and a logical zero in the rest. This
defines the starting point of the window in the X direction.
DEC(n+1)
DEC(n+2)
DEC(n+3)
DEC(n+4)
Reg(n+1)
Reg(n+2)
Reg(n+3)
Reg(n+4)
SRH
SRH
SRH
SRH
ROW(n+1)
ROW(n+2)
ROW(n+3)
ROW(n+4)
As soon as the X_SYNC signal is released, the register starts
shifting from the start position.
When no sub-sampling is required, X_SUB is inactive.
The pointer in the shift-register moves one bit at a time.
When sub-sampling is enabled, X_SUB is activated. The
shift register moves two bits at a time. Taking into account
Figure 10. Row Structure
Because every register addresses two columns at a time,
the addressable pixels range in sub-sample mode is from
zero to half the maximum number of pixels in a row (only
even values). For instance: 0, 2, 4, 6, 8 … 638.
that every register selects two columns, hence two pixels
sub-sampling results in the pattern ‘XXOOXXOO’ when
eight pixels are considered. Suppose the columns are
numbered from left to right starting with 0 (zero) and
Table 11. X–SUB-SAMPLING PATTERNS
X_SUB X_SWAP12 X_SWAP30
Sub-Sample
Pattern
sub-sampling is enabled:
0
0
0
XXXXXXXX
COL ( i )
COL (i+2)
1
0
0
XXOOXXOO
X_S WAP30
COL(i+1)
COL(i+3)
1
1
1
1
0
1
0
1
1
XOXOXOXO
OXOXOXOX
OOXXOOXX
X_SWAP12
Y ? Addressing
A
B
A
B
A
B
Column
amplifiers
For symmetry reasons, the sub-sampling modes in the
Y-direction are the same as in X-direction.
BUS _A
BUS_B
Reg(n)
Reg(n+1)
Reg(n+2)
Output
amplifier
Table 12. Y–SUB-SAMPLING PATTERNS
Y_SUB Y_SWAP12 Y_SWAP30
Sub-Sample
SYS_CLOCK 1/2
Pattern
0
0
0
XXXXXXXX
X _ SUB
X_SYNC
1
1
0
1
0
0
XXOOXXOO
XOXOXOXO
DEC(n+1)
DEC(n+2)
1
0
1
OXOXOXOX
Figure 9. Column Structure
1
1
1
OOXXOOXX
If columns 1 and 2, 5 and 6, 9 and 10 … are swapped using
the SWAP_12 switches, a normal sub-sampling pattern of
‘XOXOXOXO’ is obtained.
If columns 3 and 4, 7 and 8, 11 and 12 … are swapped
using the SWAP_30 switches, the pattern is
‘OXOXOXOX’.
If both the SWAP_12 and SWAP_30 switches are closed,
pattern ‘OOXXOOXX’ is obtained.
In normal mode, the pointer for the pixel row is shifted one
at a time.
When sub-sampling is enabled, Y_SYNC is activated.
The Y-shift register shifts 2 succeeding bits and skips the 2
next bits. This results in pattern ‘XXOOXXOO’.
Activating Y_SWAP12 results in pattern
‘XOXOXOXO’.
Activating Y_SWAP30 results in pattern
‘OXOXOXOX’.
Activating both Y_SWAP12 and Y_SWAP30 results in
pattern ‘OOXXOOXX’.
The addressable pixel range when Y-sub sampling is
enabled is: 0–1, 4–5, 8–9, 12–13, … 1020–1021
http://onsemi.com
11
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