参数资料
型号: NOII5SM1300A-QDC
厂商: ON Semiconductor
文件页数: 13/33页
文件大小: 0K
描述: SENSOR IMAGE MONO CMOS 84-LCC
标准包装: 1
象素大小: 6.7µm x 6.7µm
有源象素阵列: 1280H x 1024V
每秒帧数: 27
电源电压: 3 V ~ 4.5 V
类型: CMOS 成像
封装/外壳: 84-LCC
供应商设备封装: 84-LCC(18x18)
包装: 托盘
请注意: *
其它名称: CYII5SM1300AB-QDC
CYII5SM1300AB-QDC-ND
NOII5SM1300A
Analog-to-Digital Converter
The IBIS5-1300 has a 10-bit flash analog digital converter
running nominally at 40 Msamples/s. The ADC is
electrically separated from the image sensor. Tie the input of
the ADC (ADC_IN; pin 69) externally to the output
(PXL_OUT1; pin 28) of the output amplifier.
Table 14. ADC SPECIFICATIONS
ADC Timing
At the rising edge of SYS_CLOCK, the next pixel is fed
to the input of the output amplifier. Due to internal delays of
the SYS_CLOCK signal, it takes approximately 20 ns
before the output amplifier outputs the analog value of the
pixel, as shown in Figure 13.
The ADC converts the pixel data on the rising edge of the
Input range
Quantization
Nominal data rate
DNL (linear conversion mode)
INL (linear conversion mode)
Input capacitance
Power dissipation at 40 MHz
Conversion law
1–3 V (Note 1)
10 bits
40 Msamples/s
Typ. < 0.5 LSB
Typ. < 3 LSB
< 20 pF
Typ. 45 mA x 3.3 V = 150 mW
Linear / Gamma-corrected
ADC_CLOCK, but it takes two clock cycles before this
pixel data is at the output of the ADC. Figure 13 shows this
pipeline delay
Due to these delays, it is advisable that a variable phase
difference is foreseen between the ADC_CLOCK and the
SYS_CLOCK to tune the optimal sample moment of the
ADC.
1. The internal ADC range is typically 100 mV lower than the
external applied ADC_VHIGH and ADC_VLOW voltages due to
voltage drops over parasitic internal resistors in the ADC.
Figure 13. ADC Timing
Setting ADC Reference Voltages
The internal resistor R ADC has a value of approximately
585 W . This results in the following values for the external
resistors:
R ADC_VHIGH
Resistor
Value (O)
A DC_VHIGH ~ 2.7 V
external
R ADC_VHIGH
360
R ADC
internal
R ADC
R ADC_VLOW
585
1200
A DC_VLOW ~ 1.8 V
external
Note that the recommended ADC resistor values yield in
R ADC_VLOW
Figure 14. Internal and External ADC Connections
a conversion of the full analog output swing at unity gain
(V DARK_ANALOG < ADC_VHIGH and V LIGHT_ANALOG >
ADC_VLOW).
The values of the resistors depend on the value of R ADC .
To assure proper working of the ADC, make certain the
voltage difference between ADC_VLOW and
ADC_VHIGH is at least 1.0 V.
http://onsemi.com
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