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| 型号： | NOII5SM1300A-QDC |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/33页 |
| 文件大小： | 0K |
| 描述： | SENSOR IMAGE MONO CMOS 84-LCC |
| 标准包装： | 1 |
| 象素大小： | 6.7µm x 6.7µm |
| 有源象素阵列： | 1280H x 1024V |
| 每秒帧数： | 27 |
| 电源电压： | 3 V ~ 4.5 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 84-LCC |
| 供应商设备封装： | 84-LCC（18x18） |
| 包装： | 托盘 |
| 请注意： | * |
| 其它名称： | CYII5SM1300AB-QDC CYII5SM1300AB-QDC-ND |
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NOII5SM1300A
Image Core Operation
Image Core Operation and Signalling
Figure 8 is a functional representation of the image core
without sub-sampling and column/row swapping circuits.
Most of the signals involved are not available from the
outside because they are generated by the X-sequencer and
SS-sequencer blocks.
The integration of the pixels is controlled by internal
signals such as reset, sample, and hold which are generated
by the on-chip SS-sequencer that is controlled with the
external signals SS_START and SS_STOP. Reading out the
pixel array starts by applying a Y_START together with a
Y_CLOCK signal; internally this is followed by a
calibration sequence to calibrate the output amplifiers
(during the row blanking time). Signals necessary to do this
calibration are generated by the on-chip X-sequencer. This
calibration sequence takes typically 3.5 m s and is necessary
to remove ‘Fixed Pattern Noise’ of the pixels and of the
column amplifiers themselves by means of a double
sampling technique. After the row blanking time, the pixels
are fed to the output amplifier. The pixel rate is equal to the
SYS_CLOCK frequency.
Image Core Supply Considerations
The image sensor has several supply voltages:
VDDH is the voltage that controls the sample switches.
Do not apply a higher voltage than this to the chip.
The VDDR_LEFT voltage is the highest (nominal) reset
voltage of the pixel core.
The VDDR_RIGHT voltage is generated from the
VDDR_LEFT voltage using a circuit that is programmed
with the KNEEPOINT_LSB/MSB bits in the sequencer
register (see also Pixel reset knee ? point for multiple slope
operation (bits 8, 9, and 10) on page 17). You can disconnect
the VDDR_RIGHT pin from the circuit and apply an
external voltage to supply the multiple slope reset voltage by
setting the VDDR_RIGHT_EXT bit in the SEQUENCER
register. When no external voltage is applied
(recommended), connect the VDDR_RIGHT pin to a
capacitor (recommended value = 1 m F). VDDC is the pixel
core supply. VDDA is the image core and periphery analog
supply. VDDD is the image core and periphery digital
supply .
Note that the IBIS5-1300 image sensor has no on-chip
power rejection circuitry. As a consequence all variations on
the analog supply voltages can contribute to random
variations (noise) on the analog pixel signal, which is seen
as random noise in the image. During the camera design,
take precautions to supply the sensor with very stable supply
voltages to avoid this additional noise. The pixel array
(VDDR_LEFT, VDDH and VDDC) analog supplies are
especially vulnerable to this.
Vddreset
VDDR_LEFT
VDDH
SAMPLE
RESET
HOLD
Pixel row
VDDR _ RIGHT
Y ? left addressin g
Y _ START
Y_CLOC K
Pixel
A
Pixel column
Pixel
B
Y ? right addressing
Y _ START
Y_CLOCK
VDDC
Column amplifiers
SYS _ CLOCK
Read-pointer
BUS_ A
BUS _ B
X addressing
Output amplifier
PXL _ OUT
Figure 8. Image Core
http://onsemi.com
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| NOIL1SE3000A-GDC | 功能描述:IC IMAGE SENSOR 3MP 369-PGA RoHS:是 类别:传感器，转换器 >> 图像，相机 系列:* 标准包装:480 系列:- 象素大小:6.7µm x 6.7µm 有源象素阵列:768H x 488V 每秒帧数:52 电源电压:3.3V 类型:CMOS 成像 封装/外壳:48-QFP 供应商设备封装:48-QFP 包装:托盘 请注意:* 配用:4H2105-ND - HEADBOARD FOR KAC-004014H2104-ND - KIT EVAL FOR KAC-00401 其它名称:4H20954H2095-NDKAC-00401-CBC-LB-A0 |
| NOIL1SM0300A-QDC | 功能描述:IC IMAGE SENSOR LUPA300 48LLC RoHS:是 类别:传感器，转换器 >> 图像，相机 系列:* 标准包装:480 系列:- 象素大小:6.7µm x 6.7µm 有源象素阵列:768H x 488V 每秒帧数:52 电源电压:3.3V 类型:CMOS 成像 封装/外壳:48-QFP 供应商设备封装:48-QFP 包装:托盘 请注意:* 配用:4H2105-ND - HEADBOARD FOR KAC-004014H2104-ND - KIT EVAL FOR KAC-00401 其它名称:4H20954H2095-NDKAC-00401-CBC-LB-A0 |
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