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| 型号： | NT511740D5J-5L |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 4M X 4 EDO DRAM, 50 ns, PDSO24 |
| 封装： | 0.300 INCH, PLASTIC, SOJ-26/24 |
| 文件页数： | 16/16页 |
| 文件大小： | 129K |
| 代理商： | NT511740D5J-5L |
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000
9
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before- RAS refresh
Cycles before proper device operation is achieved.
2. VIH(min) and VlL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
4. Operation within the t RCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD >= tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL.
7.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t WCS >= t WCS(min), the cycle is an early write cycle and the data output will remain
high impedance for the duration of the cycle. If t CWD >= t CWD(min), t RWD >= t RWD(min) and tAWD >= tAWD(min),
then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If
neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be
satisfied for a read cycle.
8. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled
Write Cycle and read-modify-write cycles.
9. Operation within the tRAD (max) limit insures that tRAD(max) can be met. tRAD(max) is specified as a reference point
only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA .
10. These specifications are applied in the test mode.
11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These
Parameters should specified in test mode cycles by adding the above value to the specified value in this data sheet.
12. tASC>= 6ns, Assume t T = 2.0ns
13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
14. If tRASS>= 100us, then RAS precharge time must use tRPS instead of tRP.
15. For RAS-only refresh and burst CAS -before- RAS refresh mode, 2048(2K) cycles of burst refresh must be executed
within 32ms before and after self refresh, in order to meet refresh specification..
16. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us
immediately before and after self refresh in order to meet refresh specification.
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