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参数资料
| 型号： | NTE7134 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit Horizontal and Vertical Deflection Controller for Monitors |
| 中文描述： | 集成电路水平和垂直偏转控制器监视器 |
| 文件页数： | 10/17页 |
| 文件大小： | 89K |
| 代理商： | NTE7134 |
Functional Description:
Horizontal Sync Separator and Polarity Correction
HSYNC (Pin15) is the input for horizontal synchronization signals, which can be DC
–
coupled TTL sig-
nals (horizontal or composite sync) and AC
–
coupled negative
–
going video sync signals. Video syncs
are clamped to 1.28V and sliced at 1.4V. This results in a fixed absolute slicing level of 120mV related
to sync top.
For DC
–
coupled TTL signals the input clamping current is limited. The slicing level for TTL signals
is 1.4V.
The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and
normalize the sync polarity.
Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1
phase detector and the frequency
–
locked loop.
Vertical Sync Integrator
Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to
extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference
current at HREF (Pin28). The integrator output directly triggers the vertical oscillator. This signal is
available at VSYNC (normally vertical sync input; Pin14), which is used as an output in this mode.
Vertical Sync Slicer and Polarity Correction
Vertical sync signals (TTL) applied to VSYNC (Pin14) are sliced at 1.4V. The output signal of the sync
slicer is integrated on an internal capacitor to detect and normalize the sync polarity.
If a composite sync signal is detected at HSYNC, VSYNC is used as output for the integrated vertical
sync (e.g. for power saving applications).
Video Clamping/Vertical Blanking Generator
The video clamping/vertical blanking signal at CLBL (Pin16) is a two
–
level sandcastle pulse which
is especially suitable for video ICs, but also for direct applications in video output stages.
The upper level is the video clamping pulse, which is triggered by the trailing edge of the horizontal
sync pulse. The width of the video clamping pulse is determined by an internal monoflop.
CLSEL (Pin10) is the selection input for the position of the video clamping pulse. If CLSEL is con-
nected to GND, the clamping pulse is triggered with the trailing edge of horizontal sync. For a clamping
pulse which starts with the leading edge of horizontal sync, Pin10 must be connected to V
CC
.
The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from
the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the verti-
cal scan. This results in optimum vertical blanking.
Blanking will be activated continuously, if one of the following conditions is true:
No horizontal flyback pulses at HFLB (Pin1)
X
–
ray protection is activated
Soft start of horizontal drive (voltage at HPPL2 (Pin31) is low)
Supply voltage at V
CC
(Pin9) is low
PLL1 is unlocked while frequency
–
locked loop is in search mode
Blanking will not be activated if the horizontal sync frequency is below the valid range or there are no
sync pulses available.
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