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参数资料
| 型号： | NTE7134 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit Horizontal and Vertical Deflection Controller for Monitors |
| 中文描述： | 集成电路水平和垂直偏转控制器监视器 |
| 文件页数： | 12/17页 |
| 文件大小： | 89K |
| 代理商： | NTE7134 |
Functional Description (Cont
’
d):
Calculation of Line Frequency Range (Cont
’
d)
Thus the typical frequency range of the oscillator in this example is:
f
max
= f
S(max)
x 1.06 = 67.84kHz
f
S(min)
1.087
The resistors R
HREF
and R
HBUF
can be calculated with the following formula:
R
HREF
=74 x kHz x k
f
max
[kHz]
f
min
=
= 28.93kHz
R
HBUF
=R
HREF
x 1.19 x n
n
–
1
f
max
f
min
= 1.091k
= 1.091k
Where:
n =
= 2.35
The spread of f
min
increases with the frequency ratio
f
S(max)
f
S(min)
For higher ratios this spread can be reduced by using resistors with less tolerances.
P
LL2
Phase Detector
The PLL2 phase detector is similiar to the PLL1 detecrtor and compares the line flyback pulse at HFLB
(Pin1) with the oscillator sawtooth voltage. The PLL2 detector thus compensates for the delay in the
external horizontal deflection circuit by adjusting the phase of the HDRV (Pin7) output pulse.
The phase between horizontal flyback and horizontal sync can be controlled at HPOS (Pin30).
If HPLL2 is pulled to GND, horizontal output pulses, vertical output currents and B+ control pulses
are inhibited. This means, HDRV (Pin7), BDRV (Pin6) VOUT1 (Pin13) and VOUT2 (Pin12) are float-
ing in this state. PLL2 and the frequency
–
locked loop are disabled, and CLCB (Pin16) provides a con-
tinuous blanking signal.
This option can be used for soft start, protection and power
–
down modes. When the HPLL2 voltage
is released again, an automatic soft start sequence will be performed.
The soft start timing is determined by the filter capacitor at HPLL2 (Pin31), which is charged with a
constant current during soft start. In the beginning the horizontal driver stage generates very small
output pulses. The width of thses pulses increases with the voltage at HPLL2 until the final duty factor
is reached. At this point BDRV (Pin6), VOUT1 (Pin13 and VOUT2 (Pin12) are re
–
enabled. The volt-
age at HPLL2 continues to rise until PLL2 enters its normal operating range. The internal charge cur-
rent is now disabled. Finally PLL2 and the frequency
–
locked loop are enabled, and the continuous
blanking at CLBL is removed.
Horizontal Phase Adjustment
HPOS (Pin30) provides a linear adjustment of the relative phase between the horizontal sync and
oscillator sawtooth. Once adjusted, the relative pahse remains constant over the whole frequency
range.
Application hint:
HPOS is a current input, which provides an internal reference voltage while I
HPOS
is in the specified adjustment current range, By grounding HPOS the symmetrical control range is
forced to its center value, therefore the pahse between horizontal sync and horizontal drive pulse is
only determined by PLL2.
Output Stage for Line Drive Pulses
An open collector output stage allows direct drive of an inverting driver transistor because of a low
saturation voltage of 0.3V at 20mA. To protect the line deflection transistor, the output stage is dis-
abled (floating) for low supply voltage at V
CC
.
The duty factor of line drive pulses is slightly dependent on the actual line frequency. This ensures
optimum drive conditions over the whole frequency range.
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