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参数资料
| 型号： | ORSO42G5-3BM484C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 101/153页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
51
Figure 37. Link Header Byte
Table 10. Link Header Format
In cell mode, multiple SERDES links are used to achieve desired bandwidth. Data are cell-striped in a round-robin
fashion across two or eight links by the transmitter and then re-assembled back into a single cell stream (destrip-
ing) by the receiver. This is shown in Figure 38.
Figure 38. Multi-Link Interface - Two-Link Example
To assist with cell delineation, each link transmitter assigns sequence numbers to cells (LSEQN[6:0] bits in the Link
Header byte) before sending them out on the link. Each link increments its sequence numbers independently as
shown in Figure 38. All links reset their sequence number generator at the beginning of a SONET frame (All links
are synchronized to the start of a frame).
On the receiving side, each receiver uses the sequence numbers to verify the correct cell delineation. Since the
links were synchronized to the start of the SONET frame, all links will have cells with the same sequence number
available at the same time (although deskew needs to happen to properly align the cells). This allows the receiver
to correctly reconstruct the original cell stream.
If an unexpected sequence number is received, the receiver does not use the received value as the basis for the
next expected sequence number. Rather the old expected value is incremented by one, forming the new expected
value. An error ag is sent to the software register interface and the cell will be marked with an error. For example,
assume that the receiver expected to receive a cell with sequence number 27, but received one with sequence
number 37. The cell will be marked with an error. The receiver then expects to receive a cell with sequence number
28.
Location
Field/Description
7
Idle: Idle Cell Indicator
0: User Cell (contains valid data)
1: Idle Cell (no data in the cell payload)
6:0
LSEQ: Link Sequence Number. This value is used when aligning cells from
multiple links when doing link group multiplexing.
LIDLE
LSEQN[6:0]
LINK HEADER BYTE
Time
TRANSMITTER
Time
3
2
1
0
7
6
5
4
CELL STRIPING
0
1
LSEQ = 3
Cell = 7
LSEQ = 2
Cell = 5
LSEQ = 1
Cell = 3
LSEQ = 0
Cell = 1
Time
RECEIVER
3
2
1
0
7
6
5
4
CELL DE-STRIPING
0
1
LSEQ = 3
Cell = 6
LSEQ = 2
Cell = 4
LSEQ = 1
Cell = 2
LSEQ = 0
Cell = 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO42G5-3BMN484C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO42G5-EV | 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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