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参数资料
型号： ORSO42G5-3BM484C
厂商： Lattice Semiconductor Corporation
文件页数： 71/153页
文件大小： 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
24
Figure 10. Bit and Byte Alignment for DEMUX Block
SONET Mode Operation – Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. The basic data ows in
the SONET Mode are shown in Figure 11. At a top level, the descriptions are separated into processing in the
transmit path (FPGA to serial link) and processing in the receive path (serial link to FPGA). In general, the descrip-
tions in the next sections are written to describe SONET mode operation, although some of the “SONET logic
blocks” are also used in cell mode operation. The various processing options are selected by setting bits in control
registers and status information is written to status registers. Both types of registers can be written and/or read
from the System Bus. Memory maps and descriptions for the registers are given in Table 21 through Table 36.
Figure 11. Basic Data Flows - SONET Mode
In the SONET mode, the transmit block receives 32-bit wide data from the FPGA (DINxx) on each of its channels
along with a frame pulse (DINxx_FP) per channel and a transmit clock (TSYCLKxx). Typically this will represent a
STS-48 stream on each link. The data are rst passed through a TOH block which will generate all the timing
pulses that are required to isolate individual overhead bytes (e.g., A1, A2, B1, D1-D3, etc.). The timing pulse gener-
Time
W
O
R
D
3
W
O
R
D
2
W
O
R
D
1
W
O
R
D
0
8:32
DEMUX
W
0
W
1
W
2
W
3
Bit and Byte alignment of
LDOUT[0:7] through the
8:32 DEMUX block
to the 32-bit 77MHz data bus
7
0
7
0
31
0
Pseudo-
SONET
Processing
User
I/O
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
Configurable
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
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参数描述
ORSO42G5-3BMN484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-EV 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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