ORSO82G5-3FN680C (Lattice) PDF资料下载 Datasheet(126/153 页)

您现在的位置：买卖IC网 > PDF目录11733 > ORSO82G5-3FN680C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPBGA PDF资料下载

参数资料

型号：	ORSO82G5-3FN680C
厂商：	Lattice Semiconductor Corporation
文件页数：	126/153页
文件大小：	0K
描述：	IC TRANCEIVERS FPSC 680FPBGA
产品变化通告：	Product Discontinuation 01/Aug/2011
标准包装：	24
系列：	*

Lattice Semiconductor

ORCA ORSO42G5 and ORSO82G5 Data Sheet

Table 17. Decoding of SCHAR_CHAN

The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,

one of the channels of SERDES outputs is observed at chip ports as shown in Table 18. The channel that is

observed is also based on the decoding of SCHAR_CHAN as shown in Table 18.

Table 18. SERDES Receive Characterization Mode

Embedded Core Block RAM

There are two independent memory slices (labeled A and B) in the embedded core. Each memory slice has a

capacity of 4K words by 36 bits. These are in addition to the block RAMs found in the FPGA portion of the

ORSO42G5 and ORSO82G5. Although the memory slices are in the embedded core part of the chip, they do not

interact with the rest of the embedded core circuits, but are standalone memories designed specically to increase

RAM capacity in the ORSO42G5 and ORSO82G5 chip. They can be used by the soft IP cores implemented in the

FPGA portion of the FPSC.

A block diagram of a memory slice is shown in Figure 48. Each memory slice is organized into two sections

(labeled SRAM A and SRAM B) and has one read port, one write port and four byte-write-enable (active-low) sig-

nals. Each byte has eight data bits and a control/parity bit. The control/parity bit responds to the same byte enable

(BYTEWN_x[x]) as it’s corresponding data. No special logic such as parity checking is performed on this bit by the

core. The read data from the memory is registered so that it works as a pipelined synchronous memory block. The

minimum timing specications are shown in Figure 49 and Figure 50. Signal names and functions are summarized

later in Table 19 and follow the general Series 4 naming conventions.

SCHAR_CHAN0

SCHAR_CHAN1

Channel

SERDES Output

Chip Port

LDOUTBx[9:0]

PSCHAR_LDIO[9:0]

RBC0Bx

PSCHAR_CKIO0

RBC1Bx

PSCHAR_CKIO1

相关代理商/技术参数	参数描述
ORSO82G5-3FN680C1	功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-G2-PAC-EV	功能描述:可编程逻辑 IC 开发工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSPI4	制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-1F1156C	功能描述:FPGA - 现场可编程门阵列 16192 LUT RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSPI4-1F1156I	功能描述:FPGA - 现场可编程门阵列 16192 LUT RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256

发布紧急采购，3分钟左右您将得到回复。

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购