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| 型号： | ORT82G5-1F680I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 101/119页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
82
MPI_CLK
I
This is the PowerPC synchronous, positive-edge bus clock used for the
MPI interface. It can be
a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus
clock.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the
internal system bus for the current transaction.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
MPI_RTRY
O
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.
1
D[0:31]
I/O Selectable data bu
s width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write
transaction and driven by MPI in a read transaction.
I
D[7:0] receive conguration data during master parallel, peripheral, and slave parallel congu-
ration modes when WR is low and each pin has a pull-up enabled. During serial conguration
modes, D0 is the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After conguration, if MPI is not used, the pins are user-programmable I/O pins.
1
DP[0:3]
I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],
DP[2] for D[16:23], and DP[3] for D[24:31].
After conguration, if MPI is not used, the pins are user-programmable I/O pin.
1
DIN
I
During slave serial or master serial conguration modes, DIN accepts serial conguration data
synchronous with CCLK. During parallel conguration modes, DIN is the D0 input. During con-
guration, a pull-up is enabled.
I/O After conguration, this pin is a user-programmable I/O pin.
1
DOUT
O
During conguration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After conguration, DOUT is a user-programmable I/O pin.
1
TESTCFG
(ORT82G5 only)
I
During conguration this pin should be held high, to allow conguration to occur. A pull up is
enabled during conguration.
I/O After conguration, TESTCFG is a user programmable I/O pin.
1
1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet (ORT82G5 only) contains more information on how to con-
trol these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simulta-
neous release of all other conguration pins (and the activation of all user I/Os) is controlled by a second set of options.
Table 40. Pin Descriptions (Continued)
Symbol
I/O
Description
相关PDF资料 |
PDF描述 |
|---|---|
| MS27474E16F35S | CONN RCPT 55POS JAM NUT W/SCKT |
| CB3106A-24-7P | CONN PLUG 16POS STRAIGHT W/PINS |
| ORT82G5-1F680C | IC FPSC TRANSCEIVER 8CH 680-BGA |
| ORT42G5-2BM484C | IC FPSC TRANSCEIVER 4CH 484-BGA |
| ORT42G5-1BM484I | IC FPSC TRANSCEIVER 4CH 484-BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-1FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680C1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680I1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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