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| 型号： | ORT82G5-1F680I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 85/119页 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
68
Table 30. ORT82G5 Memory Map
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
SERDES Alarm Registers (Read Only), xx=[AA,...,BD]
30000 - AA
30010 - AB
30020 - AC
30030 - AD
30100 - BA
30110 - BB
30120 - BC
30130 - BD
[0]
Reserved
00
Reserved
[1]
LKI_xx
Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the
receive PLL is locked.
[2]
Reserved
[3]
Reserved
[4:7]
Not used
SERDES Alarm Mask Registers (Read/Write), xx=[AA,...,BD]
30001 - AA
30011 - AB
30021 - AC
30031 - AD
30101 - BA
30111 - BB
30121 - BC
30131 - BD
[0]
Reserved
FF
Reserved, must be set to 1. Set to 1 on device reset.
[1]
MLKI_xx
Mask Receive PLL Lock Indication, Channel xx.
[2]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
[3]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
[4]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
[5]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
[6]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
[7]
Reserved
Reserved, must be set to 1. Set to 1 on device reset.
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write), xx=[AA,...,BD]
30002 - AA
30012 - AB
30022 - AC
30032 - AD
30102 - BA
30112 - BB
30122 - BC
30132 - BD
[0]
TXHR_xx
00
Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1,
HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REF-
CLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on
device reset.
[1]
PWRDNT_xx
Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1,
sections of the transmit hardware are powered down to conserve power.
PWRDNT_xx = 0 on device reset.
[2]
PE0_xx
Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx
select one of three preemphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is
12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
[3]
PE1_xx
[4]
HAMP_xx
Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1,
the transmit output buffer voltage swing is limited to half its normal ampli-
tude. Otherwise, the transmit output buffer maintains its full voltage
swing. HAMP_xx = 0 on device reset.
[5]
Reserved
Reserved. Must be set to 0. Set to 0 on device reset.
[6]
Reserved
[7]
8b10bT_xx
Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1,
the 8b/10b encoder in the transmit path is enabled. Otherwise, the data
is passed unencoded. 8b10bT_xx = 0 on device reset.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-1FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680C1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680I1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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