参数资料
| 型号： | P89LPC908FD,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 20/51页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 8-SOIC |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 1 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 7.3728MHz |
| 连通性： | UART/USART |
| 外围设备： | 欠压检测/复位，LED，POR，WDT |
| 输入/输出数： | 6 |
| 程序存储器容量： | 1KB（1K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 配用： | 622-1015-ND - BOARD FOR LPC908 8-SOIC 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD |
| 其它名称： | 568-1999-1 |
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Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
27 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.6 CPU CLock (CCLK) wake-up delay
The P89LPC906/907/908 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC906) the delay is 992 OSCCLK cycles plus 60 to 100
s.
8.7 CPU CLOCK (CCLK) modication: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conguring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC906 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.9 Memory organization
The various P89LPC906/907/908 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC906/907/908 has 1 kB of on-chip Code memory.
8.9.1
Data RAM arrangement
The 128 bytes of on-chip RAM is organized as follows:
8.10 Interrupts
The P89LPC906/907/908 uses a four priority level interrupt structure. This allows
great exibility in controlling the handling of the many interrupt sources.
Table 10:
On-chip data memory usages
Type
Data RAM
Size (Bytes)
DATA
Memory that can be addressed directly and indirectly 128
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC9102 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter |
| P89LPC9102FTK | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH HVSON-10 |
| P89LPC9102FTK,115 | 功能描述:8位微控制器 -MCU PREF PART P89LPC9103FTK-G RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9102FTK-G | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9103 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter |
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