参数资料
型号: P89LPC908FD,112
厂商: NXP Semiconductors
文件页数: 33/51页
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 8-SOIC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 1
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 7.3728MHz
连通性: UART/USART
外围设备: 欠压检测/复位,LED,POR,WDT
输入/输出数: 6
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 剪切带 (CT)
配用: 622-1015-ND - BOARD FOR LPC908 8-SOIC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
其它名称: 568-1999-1
Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
39 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
may be used to wake up the CPU from Idle or Power down modes. This feature is
particularly useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
In order to set the ag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.
8.23 Watchdog timer
The watchdog timer causes a system reset when it underows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the Watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt. Figure 17 shows the
watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
afew
s to a few seconds. Please refer to the P89LPC906/907/908 User’s Manual for
more details.
8.24 Additional features
8.24.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 17. Watchdog timer in Watchdog mode (WDTE = ‘1’).
PRE2
PRE1
PRE0
WDRUN
WDTOF
WDCLK
WDCON (A7H)
CONTROL REGISTER
PRESCALER
002aaa423
SHADOW
REGISTER
FOR WDCON
8-BIT DOWN
COUNTER
WDL (C1H)
Watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
RESET
see note (1)
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