参数资料
型号: P89LPC908FD,112
厂商: NXP Semiconductors
文件页数: 9/51页
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 8-SOIC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 1
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 7.3728MHz
连通性: UART/USART
外围设备: 欠压检测/复位,LED,POR,WDT
输入/输出数: 6
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 剪切带 (CT)
配用: 622-1015-ND - BOARD FOR LPC908 8-SOIC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
其它名称: 568-1999-1
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Philips
Semiconductor
s
P89LPC906/907/908
8-bit
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.2004.
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[1]
All ports are in input only (high impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specied, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
[3]
The RSTSRC register reects the cause of the P89LPC906/907/908 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset
value is xx110000.
[4]
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset source that affects these SFRs is power-on reset.
TH0
Timer 0 high
8CH
00
00000000
TH1
Timer 1 high
8DH
00
00000000
TL0
Timer 0 low
8AH
00
00000000
TL1
Timer 1 low
8BH
00
00000000
TMOD
Timer 0 and 1 mode
89H
-
T1M1
T1M0
-
T0M1
T0M0
00
00000000
TRIM
Internal oscillator trim register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
11111111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 7:
P89LPC906 Special function registers…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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