参数资料
型号: P89V51RD2FN,112
厂商: NXP Semiconductors
文件页数: 40/80页
文件大小: 0K
描述: IC 80C51 MCU FLASH 64K 40-DIP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 9
系列: 89V
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名称: 568-2431-5
935277948112
P89V51RD2FN
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
45 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.8 Watchdog timer
The device offers a programmable Watchdog Timer (WDT) for fail safe protection against
software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT
within a user-dened time period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE = 1). The software can be
designed such that the WDT times out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment
every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used
as the reload register of the WDT.
The WDTS ag bit is set by WDT overow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 20 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control
WDT operation. During Idle mode, WDT operation is temporarily suspended, and
resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255
WDTD) × 344064 × 1/f
CLK(XTAL1)
where WDTD is the value loaded into the WDTD register and fosc is the oscillator
frequency.
Fig 19. SPI transfer format with CPHA = 1
002aaa530
MSB
S
PICLK cycle #
(for reference)
S
PICLK (CPOL = 0)
S
PICLK (CPOL = 1)
MOSI
(from master)
MISO
(from slave)
SS (to slave)
6
12
3
4
5
6
7
8
5
MSB
6543
2
1
LSB
4
3
2
1
LSB
Fig 20. Block diagram of programmable WDT
002aaa531
WDT
UPPER BYTE
WDT reset
internal reset
344064
clks
CLK (XTAL1)
external reset
WDTC
COUNTER
WDTD
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