参数资料
型号: P89V51RD2FN,112
厂商: NXP Semiconductors
文件页数: 76/80页
文件大小: 0K
描述: IC 80C51 MCU FLASH 64K 40-DIP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 9
系列: 89V
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名称: 568-2431-5
935277948112
P89V51RD2FN
PIC18F87K22 FAMILY
DS39960D-page 78
2009-2011 Microchip Technology Inc.
5.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1)
RCON Register
STKPTR Register
CM
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
11
0
RESET
instruction
0000h
u0
uu
u
Brown-out Reset
0000h
11
u
0
u
Configuration Mismatch Reset
0000h
0u
uu
u
MCLR Reset during
power-managed Run modes
0000h
uu
1u
u
MCLR Reset during power-
managed Idle modes and
Sleep mode
0000h
uu
10
u
MCLR Reset during full-power
execution
0000h
uu
u
Stack Full Reset (STVREN = 1)
0000h
uu
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
uu
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
uu
u
1
WDT time-out during full-power
or power-managed Run modes
0000h
uu
0u
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
uu
00
u
Interrupt exit from
power-managed modes
PC + 2
uu
u0
u
Legend: u
= unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
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