参数资料
型号: PC100-323-620
厂商: SIEMENS AG
英文描述: 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
中文描述: 3.3 2米x 64/72-Bit一银行内存模块3.3 4米× 64/72-Bit 2银行内存模块
文件页数: 12/17页
文件大小: 104K
代理商: PC100-323-620
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Semiconductor Group
12
SPD-Table (cont’d):
Byte#
Description
SPD Entry Value
Hex
2Mx64
-8
14
2D
04
20
10
20
10
FF
2Mx72
-8
14
2D
04
20
10
20
10
FF
4Mx64
-8
14
2D
04
20
10
20
10
FF
4Mx72
-8
14
2D
04
20
10
20
10
FF
29
30
31
32
33
34
35
Minimum RAS to CAS delay tRCD
Minimum RAS pulse width tRAS
Module Bank Density (per bank)
SDRAM input setup time
SDRAM input hold time
SDRAM data input setup time
SDRAM data input hold time
36-61 Superset information (may be used in
future)
62
SPD Revision
63
Checksum for bytes 0 - 62
64-
125
(FFh if not used)
126
Frequency Specification
127
Details of 100 MHz Support
128+ Unused storage locations
20 ns
45 ns
16 MByte
2 ns
1 ns
2 ns
1 ns
Revision 1.2
12
C9
XX
12
DB
XX
12
CA
XX
12
DC
XX
Manufacturers information (optional)
100 MHz
64
AF
FF
64
AF
FF
64
FF
FF
64
FF
FF
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