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参数资料
| 型号： | PC100-323-620 |
| 厂商： | SIEMENS AG |
| 英文描述： | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| 中文描述： | 3.3 2米x 64/72-Bit一银行内存模块3.3 4米× 64/72-Bit 2银行内存模块 |
| 文件页数： | 8/17页 |
| 文件大小： | 104K |
| 代理商： | PC100-323-620 |
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Semiconductor Group
8
AC Characteristics
3)4)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min.
max.
min.
max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
10
10
10
10
10
15
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
f
CK
–
–
100
100
–
–
100
100
–
–
100
66
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
t
AC
–
–
6
6
–
–
6
7
–
–
8
9
ns
ns
4,5)
Clock High Pulse Width
t
CH
t
CL
t
CS
t
CH
t
CKSP
3
–
3
–
3.5
–
ns
6)
Clock Low Pulse Width
3
–
3
–
3.5
–
ns
6)
Input Setup time
2
–
2
–
3
–
ns
7)
Input Hold Time
1
–
1
–
1
–
ns
7)
CKE Setup Time
(Power down mode)
2.5
–
2.5
–
3
–
ns
8)
CKE Setup Time
(Self Refresh Exit)
t
CKSR
8
–
8
–
8
–
ns
9)
Transition time (rise and fall)
t
T
1
–
1
–
1
–
ns
Common Parameters
RAS to CAS delay
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
20
–
20
–
30
–
ns
Cycle Time
70
120k
70
120k
75
120k ns
Active Command Period
45
–
45
–
45
–
ns
Precharge Time
20
–
30
–
30
–
ns
Bank to Bank Delay Time
16
–
20
–
20
–
ns
CAS to CAS delay time
(same bank)
1
–
1
–
1
–
CLK
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