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参数资料
| 型号： | PC33889 |
| 厂商： | Motorola, Inc. |
| 英文描述： | System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface |
| 中文描述： | 建兴系统基础芯片低速容错CAN接口 |
| 文件页数： | 14/30页 |
| 文件大小： | 464K |
| 代理商： | PC33889 |
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PC33889
14
PC33889
4.9.1
Wake up from wake up inputs (L0, L1) without cyclic sense:
The wake up lines are dedicated to sense external switches state and if changes occur to wake up the MCU (In sleep or stop
modes). The wake up pins are able to handle 40V DC. The internal threshold is 3V typical and these inputs can be used as input
port expander. The wake up inputs state can be read through SPI (register WUR). L0 has a lower threshold than L1 in order to
allow connection and wake up from a digital output such as a CAN physical interface for instance.
4.9.2
Cyclic sense wake up (Cyclic sense timer and wake up inputs L0, L1)
The SBC can wake up upon state change of one of the wake up input lines (L0, L1) while the external pull up or pull down
resistor of the switches associated to the wake up input lines are biased with HS1 Vsup switch. The HS1 switch is activated in
sleep or stop mode from an internal timer. Cyclic sense and Forced wake up are exclusive. If Cyclic Sense is enabled the forced
wake up can not be enabled.
4.9.3
Forced wake up
The SBC can wake up automatically after a pre determined time spent in sleep or stop mode. Forced wake up is enabled by
setting bit FWU in LPC register. Cyclic sense and Forced wake up are exclusive. If Forced wake up is enabled the Cyclic Sense
can not be enabled.
4.9.4
CAN wake up
The device can wake up from a CAN message. CAN wake up cannot be disabled.
4.9.5
SPI wake up
The device can wake up by the CSB pin in sleep or stop mode. Wake up is detected by CSB pin transition from low to high
level. In stop mode this correspond to the condition where MCU and SBC are both in Stop mode and when the application wake
up events come through the MCU.
4.9.6
System power up
At power up the device automatically wakes up.
4.10
SPI
The complete device control as well as the status report is done through a 8 bits SPI interface. Refer to SPI paragraph.
4.11
CAN
The device incorporates a low speed fault tolerant CAN physical interface. Speed rate is up to 125kBauds. Its electrical
parameters for the CANL, CANH, Rtl, Rth Rx and Tx pins are compatible with the MC33388D.
The state of the CAN interface is programmable through SPI.
4.12
Device power up, SBC wake up
After device or system power up or a wake up from sleep mode, the SBC enters into “reset mode” then into “normal request
mode”.
4.13
Battery fall early warning:
This function provides an Interrupt when the Vsup voltage is below 6.1V typical. This interrupt is maskable. An hysteresis is
included. Operation is only in Normal and Standby modes. Vbat low state reported in IOR register.
4.14
Package and thermal consideration
The device is proposed in a standard surface mount SO28 package. In order to improve the thermal performances of the
SO28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board.
4.15
Table 1: Reset and Wdogb operation
Figure below shows the reset and watchdog output operation. Reset is active at device power up and wake up. Reset is
activated in case of Vdd1 fall or watchdog not triggered. Wdogb output is active low as soon as reset goes low and stays low as
long as the watchdog is not properly re-activated by SPI.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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