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参数资料
| 型号： | PC33889 |
| 厂商： | Motorola, Inc. |
| 英文描述： | System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface |
| 中文描述： | 建兴系统基础芯片低速容错CAN接口 |
| 文件页数： | 6/30页 |
| 文件大小： | 464K |
| 代理商： | PC33889 |
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PC33889
6
PC33889
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
- MISO High Impedance
t
SOEN
t
SODIS
50
50
ns
Time from Rising Edge of SCLK to MISO
Data Valid
t
valid
50
ns
0.2 V1
≤
SO
≥
0.8V1,
C
L
=200pF
STATE MACHINE TIMING
note 1: delay starts at rising edge of CSB (end of SPI command) and start of Turn on or Turn off of HS1 or V2.
Delay between CSB low to high transition
(at end of SPI stop command) and Stop
or sleep mode activation
Tcsb-stop
18
34
us
Guaranteed by design
detected by V2 off
Interrupt low level duration
Tint
7
10
13
us
SBC in stop mode
Internal oscillator frequency
Osc-f1
100
kHz
All modes except Sleep
and Stop, guaranteed by
design
Internal low power oscillator frequency
Osc-f2
100
kHz
Sleep and Stop modes,
guaranteed by design
Watchdog period 1
Wd1
8.58
9.75
10.92
ms
Normal and standby modes
Watchdog period 2
Wd2
39.6
45
50.4
ms
Normal and standby modes
Watchdog period 3
Wd3
88
100
112
ms
Normal and standby modes
Watchdog period 4
Wd4
308
350
392
ms
Normal and standby modes
Watchdog period accuracy
F1acc
-12
12
%
Normal and standby modes
Normal request mode timeout
NRtout
308
350
392
ms
Normal request mode
Watchdog period 1 - stop
Wd1stop
6.82
9.75
12.7
ms
Stop mode
Watchdog period 2- stop
Wd2stop
31.5
45
58.5
ms
Stop mode
Watchdog period 3 - stop
Wd3stop
70
100
130
ms
Stop mode
Watchdog period 4 - stop
Wd4stop
245
350
455
ms
Stop mode
Stop mode watchdog period accuracy
F2acc
-30
30
%
Stop mode
Cyclic sense/FWU timing 1
CSFWU1
3.22
4.6
5.98
ms
Sleep and stop modes
Cyclic sense/FWU timing 2
CSFWU2
6.47
9.25
12
ms
Sleep and stop modes
Cyclic sense/FWU timing 3
CSFWU3
12.9
18.5
24
ms
Sleep and stop modes
Cyclic sense/FWU timing 4
CSFWU4
25.9
37
48.1
ms
Sleep and stop modes
Cyclic sense/FWU timing 5
CSFWU5
51.8
74
96.2
ms
Sleep and stop modes
Cyclic sense/FWU timing 6
CSFWU6
66.8
95.5
124
ms
Sleep and stop modes
Cyclic sense/FWU timing 7
CSFWU7
134
191
248
ms
Sleep and stop modes
Cyclic sense/FWU timing 8
CSFWU8
271
388
504
ms
Sleep and stop modes
Cyclic sense On time
Ton
200
350
500
us
in sleep and stop modes
threshold and condition to
be added
Cyclic sense/FWU timing accuracy
Tacc
-30
+30
%
in sleep and stop mode
Delay between SPI command and HS1
turn on (note 1)
Ts-HSon
22
us
Normal or standby mode
Vsup>9V
Delay between SPI command and HS1
turn off (note 1)
Ts-HSoff
22
us
Normal or standby mode
Vsup>9V
Delay between SPI and V2 turn on
(note 1)
Ts-V2on
9
22
us
Standby mode
Delay between SPI and V2 turn off
(note 1)
Ts-V2off
9
22
us
Normal modes
Delay between Normal Request and Nor-
mal mode, after W/D trigger command
Ts-NR2N
15
35
70
us
Normal request mode
(V
sup
From 5.5V to 18V and T
j
from -40°C to 125°C) unless otherwise noted. For all pins except can related pins
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| PC33889DP1EG | 制造商:Freescale Semiconductor 功能描述: |
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| PC33889DW | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface |
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