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参数资料
| 型号： | PC33889 |
| 厂商： | Motorola, Inc. |
| 英文描述： | System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface |
| 中文描述： | 建兴系统基础芯片低速容错CAN接口 |
| 文件页数： | 4/30页 |
| 文件大小： | 464K |
| 代理商： | PC33889 |
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PC33889
4
PC33889
Idd1 stop output current to wake up SBC
Idd1s-wu1
2
3.5
5
mA
Selectable by SPI. Default
value after reset.
Idd1 stop output current to wake up SBC
Idd1s-wu2
10
14
18
mA
Selectable by SPI
Idd1 over current wake deglitcher (with
Idd1s-wu1 selected)
Idd1-dglt1
40
75
55
us
Guaranteed by design
Idd1 over current wake deglitcher (with
Idd1s-wu2 selected)
Idd1-dglt2
150
us
Guaranteed by design
Thermal Shutdown
Tsd
160
190
°C
Normal or standby mode
Over temperature pre warning
Tpw
130
160
°C
VDDTEMP bit set
Temperature Threshold difference
Tsd-Tpw
20
40
°C
Reset threshold 1
Rst-th1
4.5
4.6
4.7
Selectable by SPI. Default
value after reset.
Reset threshold 2
Rst-th2
4.1
4.2
4.3
Selectable by SPI
Reset duration
reset-dur
0.85
1
2
ms
Vdd1 range for Reset Active
Vdd
r
1
V
Reset Delay Time
t
d
5
20
us
measured at 50% of reset sig-
nal. Guaranteed by design
Line Regulation
LR1
5
25
mV
9V<V
sup
<18, I
dd
=10mA
5.5V<V
sup
<27V, I
dd
=10mA
1mA<I
Idd
<200mA
Vsup=13.5V, I=100mA
Line Regulation
LR2
10
25
mV
Load Regulation
LD
20
50
mV
Thermal stability
ThermS
5
mV
V2 tracking voltage regulator
note 7: V2 specification with external capacitor
- option 1: C>=22uF and ESR<1O ohm
- option2: 1uF<C<22uF and ESR<10 ohm. In this case depending upon ballast transistor gain an additional resistor and capacitor network
between emitter and base of PNP ballast transistor might be required.
V2 Output Voltage
V2
0.99
1
1.01
Vdd1
I2 from 2 to 200mA
5.5V< Vsup <27V
I2 output current (for information only)
I2
200
mA
Depending upon external bal-
last transistor
V2 ctrl drive current
I2ctrl
tbd
10
tbd
mA
Logic output pins (MISO)
Low Level Output Voltage
Vol
1.0
V
I out = 1.5mA
High Level Output Voltage
Voh
Vdd1-0.9
V
I out = -250uA
Tristated MISO Leakage Current
-2
+2
uA
0V<V
miso
<Vdd
Logic input pins (MOSI, SCLK, CSB)
High Level Input Voltage
Vih
0.7Vdd1
Vdd1+0.3
V
Low Level Input Voltage
Vil
-0.3
0.3Vdd1
V
High Level Input Current on CSB
Iih
-100
-20
uA
V
i
=4V
V
i
=1V
0<V
IN
<Vdd
Low Level Input Current CSB
Iil
-100
-20
uA
MOSI, SCLK Input Current
Iin
-10
10
uA
Reset Pin (output pin only)
High Level Output current
Ioh
-250
uA
0<V
out
<0.7Vdd
5.5v<V
sup
<27V
1v<V
dd1
Low Level Output Voltage (I
0
=1.5mA)
Low Level Output Voltage (I
0
=tbd mA)
Reset pull down current
Vol
0
0.9
V
Vol
0
0.9
V
Ipdw
2.4
5
mA
Reset Duration after Vdd High
reset-dur
1
2
ms
Wdogb output pin
(V
sup
From 5.5V to 18V and T
j
from -40°C to 125°C) unless otherwise noted. For all pins except can related pins
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| PC33889DP1EG | 制造商:Freescale Semiconductor 功能描述: |
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