
Analog Integrated Circuit Device Data
Freescale Semiconductor
171
PC34708
Functional Block Requirements and Behaviors
Control Interface SPI/I2C Block Description and Application Information
ADCONT
2
R/W
DIGRESETB
0
Run ADC reads continuously when high or one time when
low. Note that the TSSTART request will have higher priority
ADHOLD
3
R/W
DIGRESETB
0
Hold the ADC reading Sequencer while saved ADC results
are read from SPI
ADSTOP0
4
R/W
DIGRESETB
0
Channel Selection to stop when complete. Always start at
000 and read up to and including this channel value.
ADSTOP1
5
R/W
DIGRESETB
0
ADSTOP2
6
R/W
DIGRESETB
0
Spare
7
R/W
DIGRESETB
0
Not available
THERM
8
R/W
DIGRESETB
0
0: NTCREF not forced on
1: Force NTCREF on
Spare
9
R/W
DIGRESETB
0
Not available
Spare
10
R/W
DIGRESETB
0
Not available
Spare
11
R/W
DIGRESETB
0
Not available
TSEN
12
R/W
DIGRESETB
0
Enable the Touch screen from low power mode.
TSSTART
13
R/W
DIGRESETB
0
Request a start of the ADC Reading Sequencer for Touch
screen readings.
TSCONT
14
R/W
DIGRESETB
0
Run ADC reads of Touch screen continuously when high or
one time when low.
TSHOLD
15
R/W
DIGRESETB
0
Hold the ADC reading Sequencer while saved Touch screen
results are read from SPI
TSSTOP0
16
R/W
DIGRESETB
0
Just like the ADSTOP above but for the Touchscreen read
programming. This will allow independent code for ADC
Sequence readings and touchscreen ADC Sequence
readings.
TSSTOP1
17
R/W
DIGRESETB
0
TSSTOP2
18
R/W
DIGRESETB
0
Spare
19
R/W
DIGRESETB
0
Not available
TSPENDET
EN
20
R/W
DIGRESETB
0
Enable the Touchscreen Pen Detection. Note that TSEN
must be off for Pen Detection.
Spare
21
R/W
DIGRESETB
0
Not available
Spare
22
R/W
DIGRESETB
0
Not available
Spare
23
R/W
DIGRESETB
0
Not available
Table 169. Register 44, ADC 1
Name
Bit #
R/W
Reset
Default
Description
ADDLY10
0
R/W
DIGRESETB
0
This will allow delay before the ADC readings.
ADDLY11
1
R/W
DIGRESETB
0
ADDLY12
2
R/W
DIGRESETB
0
ADDLY13
3
R/W
DIGRESETB
0
ADDLY20
4
R/W
DIGRESETB
0
This will allow delay between each of ADC readings in a set.
ADDLY21
5
R/W
DIGRESETB
0
ADDLY22
6
R/W
DIGRESETB
0
ADDLY23
7
R/W
DIGRESETB
0
Table 168. Register 43, ADC 0
Name
Bit #
R/W
Reset
Default
Description